Lines Matching defs:base
89 * @base: CPG register block base address
103 void __iomem *base;
127 void __iomem *base,
144 base + GET_REG_OFFSET(core->conf),
153 base + GET_REG_OFFSET(core->conf),
166 void __iomem *base,
174 base + GET_REG_OFFSET(core->conf),
210 writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
212 ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
219 writel(bitmask | ((index + 1) << shift), priv->base + off);
221 ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
237 u32 val = readl(priv->base + GET_REG_OFFSET(hwdata->conf));
253 void __iomem *base,
375 priv->base + CPG_PL5_SDIV);
464 priv->base + CPG_OTHERFUNC1_REG);
474 return readl(priv->base + GET_REG_OFFSET(hwdata->conf));
590 writel(CPG_SIPLL5_STBY_RESETB_WEN, priv->base + CPG_SIPLL5_STBY);
591 ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
600 (params.pl5_refdiv << 8), priv->base + CPG_SIPLL5_CLK1);
603 writel((params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);
607 priv->base + CPG_SIPLL5_CLK4);
610 writel(params.pl5_spread, priv->base + CPG_SIPLL5_CLK5);
615 priv->base + CPG_SIPLL5_STBY);
618 ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
666 CPG_SIPLL5_STBY_RESETB, priv->base + CPG_SIPLL5_STBY);
686 void __iomem *base;
703 val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
704 val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
719 void __iomem *base,
745 pll_clk->base = base;
834 priv->base, priv);
841 priv->base, priv);
844 clk = rzg2l_cpg_mux_clk_register(core, priv->base, priv);
847 clk = rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv);
916 writel(value, priv->base + CLK_ON_R(reg));
926 error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,
930 priv->base + CLK_ON_R(reg));
991 value = readl(priv->base + CLK_MON_R(clock->off));
993 value = readl(priv->base + clock->off);
1120 writel(value, priv->base + CLK_RST_R(reg));
1133 return readl_poll_timeout_atomic(priv->base + reg, value,
1150 writel(value, priv->base + CLK_RST_R(reg));
1163 return readl_poll_timeout_atomic(priv->base + reg, value,
1198 return !!(readl(priv->base + reg) & bitmask);
1362 priv->base = devm_platform_ioremap_resource(pdev, 0);
1363 if (IS_ERR(priv->base))
1364 return PTR_ERR(priv->base);