Lines Matching defs:clock
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
138 * @notifiers: Notifier chain to save/restore clock state for system resume
177 * struct mstp_clock - MSTP gating clock
179 * @index: MSTP clock number
192 struct mstp_clock *clock = to_mstp_clock(hw);
193 struct cpg_mssr_priv *priv = clock->priv;
194 unsigned int reg = clock->index / 32;
195 unsigned int bit = clock->index % 32;
252 struct mstp_clock *clock = to_mstp_clock(hw);
253 struct cpg_mssr_priv *priv = clock->priv;
257 value = readb(priv->base + priv->control_regs[clock->index / 32]);
259 value = readl(priv->base + priv->status_regs[clock->index / 32]);
261 return !(value & BIT(clock->index % 32));
286 dev_err(dev, "Invalid %s clock index %u\n", type,
303 dev_err(dev, "Invalid %s clock index %u\n", type,
311 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
316 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
319 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
338 /* Skip NULLified clock */
385 dev_err(dev, "%s has unsupported core clock type %u\n",
393 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
398 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
406 struct mstp_clock *clock = NULL;
420 /* Skip NULLified clock */
430 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
431 if (!clock) {
443 clock->index = id - priv->num_core_clks;
444 clock->priv = priv;
445 clock->hw.init = &init;
449 cpg_mstp_clock_is_enabled(&clock->hw)) {
456 clk = clk_register(NULL, &clock->hw);
460 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
462 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
466 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
468 kfree(clock);
512 dev_dbg(dev, "CPG/MSSR clock domain not yet available\n");
516 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
615 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */