Lines Matching defs:mult
48 #define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */
74 unsigned int mult;
76 mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1;
78 return parent_rate * mult * 2;
84 unsigned int min_mult, max_mult, mult;
93 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
94 mult = clamp(mult, min_mult, max_mult);
96 req->rate = prate * mult;
104 unsigned int mult;
107 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2);
108 mult = clamp(mult, 1U, 256U);
114 FIELD_PREP(CPG_PLLxCR0_NI, mult - 1));
199 unsigned int mult;
203 mult = 32 - (val >> __ffs(zclk->mask));
205 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
213 unsigned int min_mult, max_mult, mult;
233 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
234 mult = clamp(mult, min_mult, max_mult);
236 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
244 unsigned int mult;
247 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
249 mult = clamp(mult, 1U, 32U);
254 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
337 unsigned int mult = 1;
351 mult = cpg_pll_config->pll1_mult;
365 mult = cpg_pll_config->pll2_mult;
370 mult = cpg_pll_config->pll3_mult;
375 mult = cpg_pll_config->pll4_mult;
380 mult = cpg_pll_config->pll5_mult;
385 mult = cpg_pll_config->pll6_mult;
391 mult = (((value >> 24) & 0x7f) + 1) * 2;
423 mult = 1;
453 __clk_get_name(parent), 0, mult, div);