Lines Matching refs:pll_clk
55 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK;
62 return parent_rate * mult * pll_clk->fixed_mult;
68 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
72 prate = req->best_parent_rate * pll_clk->fixed_mult;
88 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
95 val = readl(pll_clk->pllcr_reg);
98 writel(val, pll_clk->pllcr_reg);
101 if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
124 struct cpg_pll_clk *pll_clk;
128 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
129 if (!pll_clk)
137 pll_clk->hw.init = &init;
138 pll_clk->pllcr_reg = base + offset;
139 pll_clk->pllecr_reg = base + CPG_PLLECR;
140 pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
141 pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
143 clk = clk_register(NULL, &pll_clk->hw);
145 kfree(pll_clk);