Lines Matching refs:parent
157 * clk->rate = (parent->rate * mult / 32 ) / fixed_div
158 * parent - fixed parent. No clk_set_parent support
198 /* Set parent rate to initial value for normal modes */
201 /* Set increased parent rate for boost modes */
336 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
352 const struct clk *parent;
357 parent = clks[core->parent & 0xffff]; /* some types use high bits */
358 if (IS_ERR(parent))
359 return ERR_CAST(parent);
372 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
386 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
407 __clk_get_name(parent), notifiers);
411 __clk_get_name(parent));
430 parent = clks[cpg_clk_extalr];
439 /* Select parent clock of RCLK by MD28 */
441 parent = clks[cpg_clk_extalr];
452 parent = clks[core->parent >> 16];
453 if (IS_ERR(parent))
454 return ERR_CAST(parent);
461 return cpg_z_clk_register(core->name, __clk_get_name(parent),
465 return cpg_zg_clk_register(core->name, __clk_get_name(parent),
483 parent = clks[core->parent >> 16];
484 if (IS_ERR(parent))
485 return ERR_CAST(parent);
492 __clk_get_name(parent), 0,
513 parent = clks[core->parent >> 16];
514 if (IS_ERR(parent))
515 return ERR_CAST(parent);
527 __clk_get_name(parent), notifiers);
531 __clk_get_name(parent));
538 __clk_get_name(parent), 0, mult, div);