Lines Matching defs:value
198 /* Set parent rate to initial value for normal modes */
247 * Since this value might be dependent on external xtal rate, pll1
249 * "super" safe value.
355 u32 value;
399 * the multiplier value.
401 value = readl(base + CPG_PLL4CR);
402 mult = (((value >> 24) & 0x7f) + 1) * 2;
427 value = readl(csn->reg) & 0x3f;
431 value |= CPG_RCKCR_CKSEL;
434 writel(value, csn->reg);
500 * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
503 value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
505 switch (value) {