Lines Matching defs:mult
56 unsigned int mult;
60 mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1;
62 return parent_rate * mult * pll_clk->fixed_mult;
69 unsigned int min_mult, max_mult, mult;
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
79 mult = clamp(mult, min_mult, max_mult);
81 req->rate = prate * mult;
89 unsigned int mult, i;
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
93 mult = clamp(mult, 1U, 128U);
97 val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
119 unsigned int mult,
140 pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
157 * clk->rate = (parent->rate * mult / 32 ) / fixed_div
179 unsigned int mult;
183 mult = 32 - (val >> __ffs(zclk->mask));
185 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
193 unsigned int min_mult, max_mult, mult;
213 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
214 mult = clamp(mult, min_mult, max_mult);
216 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
224 unsigned int mult;
227 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
229 mult = clamp(mult, 1U, 32U);
234 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
353 unsigned int mult = 1;
376 mult = cpg_pll_config->pll1_mult;
390 mult = cpg_pll_config->pll3_mult;
402 mult = (((value >> 24) & 0x7f) + 1) * 2;
457 mult = 1;
538 __clk_get_name(parent), 0, mult, div);