Lines Matching refs:gate
62 * @gate: clock enable/disable
69 * which controls some aspect of clock gating. The @gate field
82 struct regbit gate, reset, ready, midle;
88 K_GATE = 0, /* gate which enable/disable */
104 * @gate: clock enable/disable
114 * @g1: 1st source gate (clock enable/disable)
116 * @g2: 2nd source gate (clock enable/disable)
131 struct r9a06g032_gate gate;
154 .gate = _clk, \
167 .gate = I_GATE(__VA_ARGS__) \
175 .gate = I_GATE(__VA_ARGS__) \
628 * parent for a clock, but also the gate it's supposed to use.
719 * This implements the R9A06G032 clock gate 'driver'. We cannot use the system's
720 * clock gate framework as the gates on the R9A06G032 have a special enabling
728 struct r9a06g032_gate gate;
817 WARN_ON(!g->gate.reg && !g->gate.bit);
820 clk_rdesc_set(clocks, g->gate, on);
845 r9a06g032_clk_gate_set(g->clocks, &g->gate, 1);
853 r9a06g032_clk_gate_set(g->clocks, &g->gate, 0);
860 /* if clock is in reset, the gate might be on, and still not 'be' on */
861 if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset))
864 return clk_rdesc_get(g->clocks, g->gate.gate);
894 g->gate = desc->gate;
1090 * active gate (and turn the others off) and force a recalculation of the rates.
1094 * that knows which gate to poke at, depending on the parent's bit position.
1139 /* allocate the gate */
1171 struct r9a06g032_gate gate[2];
1182 /* we always turn off the 'other' gate, regardless */
1183 r9a06g032_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
1184 r9a06g032_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
1191 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
1193 r9a06g032_clk_dualgate_setenable(gate, 1);
1200 struct r9a06g032_clk_dualgate *gate = to_clk_dualgate(hw);
1202 r9a06g032_clk_dualgate_setenable(gate, 0);
1210 return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
1229 /* allocate the gate */
1236 g->gate[0].gate = desc->dual.g1;
1237 g->gate[0].reset = desc->dual.r1;
1238 g->gate[1].gate = desc->dual.g2;
1239 g->gate[1].reset = desc->dual.r2;