Lines Matching defs:GATE
62 #define GATE(_id, _name, _pname, _shift) \
71 GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
72 GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
73 GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
74 GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
75 GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
76 GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
77 GATE(MT7621_CLK_GDMA, "gdma", "bus", BIT(14)),
78 GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
79 GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
80 GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),
81 GATE(MT7621_CLK_SPI, "spi", "bus", BIT(18)),
82 GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)),
83 GATE(MT7621_CLK_UART2, "uart2", "50m", BIT(20)),
84 GATE(MT7621_CLK_UART3, "uart3", "50m", BIT(21)),
85 GATE(MT7621_CLK_ETH, "eth", "50m", BIT(23)),
86 GATE(MT7621_CLK_PCIE0, "pcie0", "125m", BIT(24)),
87 GATE(MT7621_CLK_PCIE1, "pcie1", "125m", BIT(25)),
88 GATE(MT7621_CLK_PCIE2, "pcie2", "125m", BIT(26)),
89 GATE(MT7621_CLK_CRYPTO, "crypto", "250m", BIT(29)),
90 GATE(MT7621_CLK_SHXC, "shxc", "50m", BIT(30))