Lines Matching defs:rcg
21 #include "clk-rcg.h"
46 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
47 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
48 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
49 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
66 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
70 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
79 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
87 if (cfg == rcg->parent_map[i].cfg)
97 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
101 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
111 static int update_config(struct clk_rcg2 *rcg)
115 struct clk_hw *hw = &rcg->clkr.hw;
118 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
125 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
133 WARN(1, "%s: rcg didn't update its configuration.", name);
139 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
141 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
143 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
148 return update_config(rcg);
173 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
176 if (rcg->mnd_width) {
177 mask = BIT(rcg->mnd_width) - 1;
178 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
180 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
188 mask = BIT(rcg->hid_width) - 1;
198 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
201 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
212 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
229 index = qcom_find_src_index(hw, rcg->parent_map, f->src);
266 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
268 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
274 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
276 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
279 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
283 struct clk_hw *hw = &rcg->clkr.hw;
284 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
289 if (rcg->mnd_width && f->n) {
290 mask = BIT(rcg->mnd_width) - 1;
291 ret = regmap_update_bits(rcg->clkr.regmap,
292 RCG_M_OFFSET(rcg), mask, f->m);
296 ret = regmap_update_bits(rcg->clkr.regmap,
297 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));
310 ret = regmap_update_bits(rcg->clkr.regmap,
311 RCG_D_OFFSET(rcg), mask, not2d_val);
316 mask = BIT(rcg->hid_width) - 1;
319 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
320 if (rcg->mnd_width && f->n && (f->m != f->n))
322 if (rcg->hw_clk_ctrl)
331 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
336 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
340 ret = __clk_rcg2_configure(rcg, f, &cfg);
344 ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg);
348 return update_config(rcg);
354 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
359 f = qcom_find_freq_floor(rcg->freq_tbl, rate);
362 f = qcom_find_freq(rcg->freq_tbl, rate);
371 return clk_rcg2_configure(rcg, f);
400 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
403 if (!rcg->mnd_width) {
410 regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), ¬2d);
411 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
412 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
421 mask = BIT(rcg->mnd_width) - 1;
436 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
441 if (!rcg->mnd_width)
444 mask = BIT(rcg->mnd_width) - 1;
446 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
447 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
448 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
474 ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask,
479 return update_config(rcg);
545 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
546 struct freq_tbl f = *rcg->freq_tbl;
551 u32 mask = BIT(rcg->hid_width) - 1;
567 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
575 return clk_rcg2_configure(rcg, &f);
591 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
592 const struct freq_tbl *f = rcg->freq_tbl;
596 u32 mask = BIT(rcg->hid_width) - 1;
598 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
617 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
645 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
646 const struct freq_tbl *f = rcg->freq_tbl;
647 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
649 u32 mask = BIT(rcg->hid_width) - 1;
669 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
670 struct freq_tbl f = *rcg->freq_tbl;
672 u32 mask = BIT(rcg->hid_width) - 1;
679 return clk_rcg2_configure(rcg, &f);
703 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
705 u32 mask = BIT(rcg->hid_width) - 1;
726 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
730 u32 mask = BIT(rcg->hid_width) - 1;
738 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
743 if (cfg == rcg->parent_map[i].cfg) {
744 f.src = rcg->parent_map[i].src;
745 return clk_rcg2_configure(rcg, &f);
805 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
810 u32 mask = BIT(rcg->hid_width) - 1;
814 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
819 if (cfg == rcg->parent_map[i].cfg) {
820 f.src = rcg->parent_map[i].src;
831 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
839 return clk_rcg2_configure(rcg, &f);
937 struct clk_rcg2 *rcg = &cgfx->rcg;
941 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
946 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
950 return update_config(rcg);
977 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
981 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
1000 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1002 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
1009 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1016 ret = clk_rcg2_configure(rcg, f);
1026 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1029 f = qcom_find_freq(rcg->freq_tbl, rate);
1039 return __clk_rcg2_configure(rcg, f, &rcg->parked_cfg);
1052 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1064 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg);
1068 ret = update_config(rcg);
1077 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1083 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
1095 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
1096 rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
1098 update_config(rcg);
1105 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1107 /* If the shared rcg is parked use the cached cfg instead */
1109 return __clk_rcg2_get_parent(hw, rcg->parked_cfg);
1116 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1118 /* If the shared rcg is parked only update the cached cfg */
1120 rcg->parked_cfg &= ~CFG_SRC_SEL_MASK;
1121 rcg->parked_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
1132 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1134 /* If the shared rcg is parked use the cached cfg instead */
1136 return __clk_rcg2_recalc_rate(hw, parent_rate, rcg->parked_cfg);
1157 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1163 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
1165 mask = BIT(rcg->hid_width) - 1;
1175 if (src == rcg->parent_map[i].cfg) {
1176 f->src = rcg->parent_map[i].src;
1177 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
1185 mask = BIT(rcg->mnd_width) - 1;
1186 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
1191 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
1202 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
1211 rcg->freq_tbl = freq_tbl;
1214 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
1222 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1225 if (!rcg->freq_tbl) {
1226 ret = clk_rcg2_dfs_populate_freq_table(rcg);
1240 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1243 regmap_read(rcg->clkr.regmap,
1244 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
1248 if (rcg->freq_tbl)
1249 return rcg->freq_tbl[level].freq;
1258 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
1261 mask = BIT(rcg->hid_width) - 1;
1269 mask = BIT(rcg->mnd_width) - 1;
1270 regmap_read(rcg->clkr.regmap,
1271 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
1274 regmap_read(rcg->clkr.regmap,
1275 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
1294 struct clk_rcg2 *rcg = data->rcg;
1299 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
1313 rcg->freq_tbl = NULL;
1336 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1338 u32 mask = BIT(rcg->hid_width) - 1;
1344 GENMASK(rcg->mnd_width - 1, 0),
1345 GENMASK(rcg->mnd_width - 1, 0), &den, &num);
1350 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
1356 if (cfg == rcg->parent_map[i].cfg) {
1357 f.src = rcg->parent_map[i].src;
1374 return clk_rcg2_configure(rcg, &f);
1386 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1392 GENMASK(rcg->mnd_width - 1, 0),
1393 GENMASK(rcg->mnd_width - 1, 0), &den, &num);