Lines Matching defs:rcg
15 #include "clk-rcg.h"
39 struct clk_rcg *rcg = to_clk_rcg(hw);
44 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
47 ns = ns_to_src(&rcg->s, ns);
49 if (ns == rcg->s.parent_map[i].cfg)
58 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
60 bank &= BIT(rcg->mux_sel_bit);
66 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
73 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
76 bank = reg_to_bank(rcg, reg);
77 s = &rcg->s[bank];
79 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
96 struct clk_rcg *rcg = to_clk_rcg(hw);
99 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
100 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
101 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
198 static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
207 bool banked_mn = !!rcg->mn[1].width;
208 bool banked_p = !!rcg->p[1].pre_div_width;
209 struct clk_hw *hw = &rcg->clkr.hw;
213 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
216 bank = reg_to_bank(rcg, reg);
219 ns_reg = rcg->ns_reg[new_bank];
220 ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
225 mn = &rcg->mn[new_bank];
226 md_reg = rcg->md_reg[new_bank];
229 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
233 ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
237 ret = regmap_write(rcg->clkr.regmap, md_reg, md);
241 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
246 if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
248 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
253 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg,
260 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
266 p = &rcg->p[new_bank];
270 s = &rcg->s[new_bank];
275 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
280 ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
283 reg ^= BIT(rcg->mux_sel_bit);
284 ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
293 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
297 bool banked_mn = !!rcg->mn[1].width;
298 bool banked_p = !!rcg->p[1].pre_div_width;
300 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
301 bank = reg_to_bank(rcg, reg);
303 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
306 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
307 f.m = md_to_m(&rcg->mn[bank], md);
308 f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
312 f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
314 f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index);
315 return configure_bank(rcg, &f);
344 struct clk_rcg *rcg = to_clk_rcg(hw);
346 struct mn *mn = &rcg->mn;
348 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
349 pre_div = ns_to_pre_div(&rcg->p, ns);
351 if (rcg->mn.width) {
352 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
356 if (rcg->clkr.enable_reg != rcg->ns_reg)
357 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
369 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
373 bool banked_p = !!rcg->p[1].pre_div_width;
374 bool banked_mn = !!rcg->mn[1].width;
376 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
377 bank = reg_to_bank(rcg, reg);
379 regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
383 mn = &rcg->mn[bank];
384 regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
388 if (rcg->ns_reg[0] != rcg->ns_reg[1])
394 pre_div = ns_to_pre_div(&rcg->p[bank], ns);
438 struct clk_rcg *rcg = to_clk_rcg(hw);
440 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req,
441 rcg->s.parent_map);
447 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
452 regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
453 bank = reg_to_bank(rcg, reg);
454 s = &rcg->s[bank];
456 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map);
462 struct clk_rcg *rcg = to_clk_rcg(hw);
463 const struct freq_tbl *f = rcg->freq_tbl;
465 int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src);
474 static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
477 struct mn *mn = &rcg->mn;
481 if (rcg->mn.reset_in_cc)
482 reset_reg = rcg->clkr.enable_reg;
484 reset_reg = rcg->ns_reg;
486 if (rcg->mn.width) {
488 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask);
490 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md);
492 regmap_write(rcg->clkr.regmap, rcg->md_reg, md);
494 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
496 if (rcg->clkr.enable_reg != rcg->ns_reg) {
497 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
499 regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
505 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
508 ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns);
509 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
511 regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0);
519 struct clk_rcg *rcg = to_clk_rcg(hw);
522 f = qcom_find_freq(rcg->freq_tbl, rate);
526 return __clk_rcg_set_rate(rcg, f);
532 struct clk_rcg *rcg = to_clk_rcg(hw);
535 f = qcom_find_freq_floor(rcg->freq_tbl, rate);
539 return __clk_rcg_set_rate(rcg, f);
545 struct clk_rcg *rcg = to_clk_rcg(hw);
547 return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
565 struct clk_rcg *rcg = to_clk_rcg(hw);
570 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
574 src = ns_to_src(&rcg->s, ns);
575 f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1;
578 if (src == rcg->s.parent_map[i].cfg) {
579 f.src = rcg->s.parent_map[i].src;
580 return __clk_rcg_set_rate(rcg, &f);
633 struct clk_rcg *rcg = to_clk_rcg(hw);
641 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
645 src = ns_to_src(&rcg->s, ns);
648 if (src == rcg->s.parent_map[i].cfg) {
649 f.src = rcg->s.parent_map[i].src;
668 return __clk_rcg_set_rate(rcg, &f);
683 struct clk_rcg *rcg = to_clk_rcg(hw);
684 int pre_div_max = BIT(rcg->p.pre_div_width);
707 struct clk_rcg *rcg = to_clk_rcg(hw);
709 int pre_div_max = BIT(rcg->p.pre_div_width);
717 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
721 ns = ns_to_src(&rcg->s, ns);
724 if (ns == rcg->s.parent_map[i].cfg) {
725 f.src = rcg->s.parent_map[i].src;
734 return __clk_rcg_set_rate(rcg, &f);
760 struct clk_rcg *rcg = to_clk_rcg(hw);
765 f = qcom_find_freq(rcg->freq_tbl, rate);
770 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
771 ret = __clk_rcg_set_rate(rcg, f);
774 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
781 struct clk_rcg *rcg = to_clk_rcg(hw);
785 return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm);
790 struct clk_rcg *rcg = to_clk_rcg(hw);
794 regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0);
799 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
802 f = qcom_find_freq(rcg->freq_tbl, rate);
806 return configure_bank(rcg, f);