Lines Matching defs:mode
245 /* Two NS registers means mode control is in NS register */
326 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 pre_div)
331 if (mode) {
345 u32 pre_div, m = 0, n = 0, ns, md, mode = 0;
355 /* MN counter mode is in hw.enable_reg sometimes */
357 regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode);
359 mode = ns;
360 mode = reg_to_mnctr_mode(mn, mode);
363 return calc_rate(parent_rate, m, n, mode, pre_div);
370 u32 m, n, pre_div, ns, md, mode, reg;
380 m = n = pre_div = mode = 0;
387 /* Two NS registers means mode control is in NS register */
390 mode = reg_to_mnctr_mode(mn, reg);
396 return calc_rate(parent_rate, m, n, mode, pre_div);
495 /* MN counter mode is in hw.enable_reg sometimes */