Lines Matching refs:rate
572 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
578 quotient = rate;
584 return rate;
600 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
606 if (rate >= v->min_freq && rate <= v->max_freq)
694 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
703 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
704 vco = alpha_pll_find_vco(pll, rate);
733 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
736 return __clk_alpha_pll_set_rate(hw, rate, prate,
740 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
743 return __clk_alpha_pll_set_rate(hw, rate, prate,
747 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
755 rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
756 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
757 return rate;
762 return clamp(rate, min_freq, max_freq);
779 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
785 quotient = rate;
791 return rate;
815 u64 rate = parent_rate, tmp;
842 return alpha_huayra_pll_calc_rate(rate, l, alpha);
847 rate *= l;
853 rate -= tmp;
857 rate += tmp;
860 return rate;
863 return alpha_huayra_pll_calc_rate(rate, l, alpha);
866 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
872 rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
909 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
914 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
1098 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1109 return divider_round_rate(hw, rate, prate, table,
1114 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1127 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1132 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1139 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1296 * Due to limited number of bits for fractional rate programming, the
1297 * rounded up rate could be marginally higher than the requested rate.
1300 unsigned long rrate, unsigned long rate)
1302 unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1304 if (rrate > rate_margin || rrate < rate) {
1305 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1306 clk_hw_get_name(hw), rrate, rate, rate_margin);
1313 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1322 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1324 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1456 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1461 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1466 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1473 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1494 unsigned long rate, unsigned long *prate)
1498 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1503 unsigned long rate, unsigned long parent_rate)
1519 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1627 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1636 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1638 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1674 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1677 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1727 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1736 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1737 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1862 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1865 return __alpha_pll_trion_set_rate(hw, rate, prate,
1870 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1896 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1909 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1912 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
2047 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2057 rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
2059 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2269 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2272 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2344 static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2352 rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2353 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2354 return rate;
2359 return clamp(rate, min_freq, max_freq);
2431 req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate,
2437 static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2445 rate = alpha_pll_round_rate(rate, prate, &l, &a, ALPHA_REG_BITWIDTH);
2484 unsigned long rate,
2492 rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);