Lines Matching refs:pll
13 #include "clk-alpha-pll.h"
292 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
298 const char *name = clk_hw_get_name(&pll->clkr.hw);
300 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
305 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
320 #define wait_for_pll_enable_active(pll) \
321 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
323 #define wait_for_pll_enable_lock(pll) \
324 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
326 #define wait_for_zonda_pll_freq_lock(pll) \
327 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
329 #define wait_for_pll_disable(pll) \
330 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
332 #define wait_for_pll_offline(pll) \
333 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
335 #define wait_for_pll_update(pll) \
336 wait_for_pll(pll, PLL_UPDATE, 1, "update")
338 #define wait_for_pll_update_ack_set(pll) \
339 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
341 #define wait_for_pll_update_ack_clear(pll) \
342 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
351 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
356 regmap_write(regmap, PLL_L_VAL(pll), config->l);
357 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
358 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
360 if (pll_has_64bit_config(pll))
361 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
364 if (pll_alpha_width(pll) > 32)
365 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
385 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
388 regmap_update_bits(regmap, PLL_TEST_CTL(pll),
392 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
396 regmap_update_bits(regmap, PLL_TEST_CTL_U(pll),
400 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
403 if (pll->flags & SUPPORTS_FSM_MODE)
404 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
411 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
414 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
420 if (pll->flags & SUPPORTS_OFFLINE_REQ)
423 ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
430 return wait_for_pll_enable_active(pll);
436 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
439 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
443 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
444 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
449 ret = wait_for_pll_offline(pll);
455 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
460 wait_for_pll_disable(pll);
466 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
469 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
489 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
493 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
502 return wait_for_pll_enable_active(pll);
509 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
521 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
526 ret = wait_for_pll_enable_lock(pll);
530 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
541 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
544 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
555 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
562 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
600 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
602 const struct pll_vco *v = pll->vco_table;
603 const struct pll_vco *end = v + pll->num_vco;
617 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
618 u32 alpha_width = pll_alpha_width(pll);
620 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
622 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
624 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
626 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
641 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
646 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
649 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
663 ret = wait_for_pll_update_ack_set(pll);
667 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
669 ret = wait_for_pll_update(pll);
674 ret = wait_for_pll_update_ack_clear(pll);
684 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
687 if (!is_enabled(&pll->clkr.hw) ||
688 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
691 return __clk_alpha_pll_update_latch(pll);
698 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
700 u32 l, alpha_width = pll_alpha_width(pll);
704 vco = alpha_pll_find_vco(pll, rate);
705 if (pll->vco_table && !vco) {
706 pr_err("%s: alpha pll not in a valid vco range\n",
711 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
717 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
719 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
722 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
727 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
730 return clk_alpha_pll_update_latch(pll, is_enabled);
750 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
751 u32 l, alpha_width = pll_alpha_width(pll);
756 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
759 min_freq = pll->vco_table[0].min_freq;
760 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
816 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
819 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
820 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
823 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
869 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
874 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
877 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
890 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
893 return wait_for_pll_enable_lock(pll);
896 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
897 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
900 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
903 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
917 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
923 ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
924 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
933 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
935 return trion_pll_is_enabled(pll, pll->clkr.regmap);
940 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
941 struct regmap *regmap = pll->clkr.regmap;
945 ret = regmap_read(regmap, PLL_MODE(pll), &val);
954 return wait_for_pll_enable_active(pll);
958 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
960 ret = wait_for_pll_enable_lock(pll);
965 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
971 return regmap_update_bits(regmap, PLL_MODE(pll),
977 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
978 struct regmap *regmap = pll->clkr.regmap;
982 ret = regmap_read(regmap, PLL_MODE(pll), &val);
993 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
998 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1004 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1005 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1011 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1012 u32 l, frac, alpha_width = pll_alpha_width(pll);
1014 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1015 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
1070 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1073 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1076 ctl &= PLL_POST_DIV_MASK(pll);
1101 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1104 if (pll->width == 2)
1110 pll->width, CLK_DIVIDER_POWER_OF_TWO);
1117 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1120 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1123 ctl &= BIT(pll->width) - 1;
1135 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1141 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1142 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1159 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1164 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1165 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1166 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1168 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1170 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1172 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1174 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1176 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1182 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1185 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1186 regmap_update_bits(regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1189 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1192 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1199 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1201 struct regmap *regmap = pll->clkr.regmap;
1203 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1212 return wait_for_pll_enable_active(pll);
1215 ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1223 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1227 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1231 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1236 ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1240 ret = wait_for_pll_enable_lock(pll);
1244 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1249 return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1256 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1258 struct regmap *regmap = pll->clkr.regmap;
1260 ret = regmap_read(regmap, PLL_MODE(pll), &val);
1270 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1275 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1280 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1286 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1287 u32 l, frac, alpha_width = pll_alpha_width(pll);
1289 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1290 regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1316 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1317 u32 l, alpha_width = pll_alpha_width(pll);
1328 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1329 regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1331 return __clk_alpha_pll_update_latch(pll);
1336 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1340 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1346 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1354 vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1356 pr_err("%s: alpha pll not in a valid vco range\n", name);
1360 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1361 pll->vco_table[0].max_freq) * 54, 100);
1375 regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1380 pr_err("%s: alpha pll calibration failed\n", name);
1412 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1416 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1420 val >>= pll->post_div_shift;
1421 val &= BIT(pll->width) - 1;
1423 for (i = 0; i < pll->num_post_div; i++) {
1424 if (pll->post_div_table[i].val == val) {
1425 div = pll->post_div_table[i].div;
1436 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1437 struct regmap *regmap = pll->clkr.regmap;
1440 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1442 val >>= pll->post_div_shift;
1443 val &= PLL_POST_DIV_MASK(pll);
1445 for (i = 0; i < pll->num_post_div; i++) {
1446 if (pll->post_div_table[i].val == val) {
1447 div = pll->post_div_table[i].div;
1459 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1461 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1462 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1469 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1470 struct regmap *regmap = pll->clkr.regmap;
1474 for (i = 0; i < pll->num_post_div; i++) {
1475 if (pll->post_div_table[i].div == div) {
1476 val = pll->post_div_table[i].val;
1481 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1482 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1496 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1498 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1499 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1505 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1512 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1520 for (i = 0; i < pll->num_post_div; i++) {
1521 if (pll->post_div_table[i].div == div) {
1522 val = pll->post_div_table[i].val;
1527 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1528 (BIT(pll->width) - 1) << pll->post_div_shift,
1529 val << pll->post_div_shift);
1540 * clk_trion_pll_configure - configure the trion pll
1542 * @pll: clk alpha pll
1544 * @config: configuration to apply for pll
1546 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1553 if (trion_pll_is_enabled(pll, regmap)) {
1558 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1559 regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1560 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1561 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1563 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1565 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1567 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1569 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1571 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1573 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1575 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1577 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1580 regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1584 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1587 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1590 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1600 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1605 regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1630 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1632 u32 val, l, alpha_width = pll_alpha_width(pll);
1642 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1643 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1646 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1652 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1659 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1664 ret = wait_for_pll_enable_lock(pll);
1709 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1712 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1713 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1714 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1716 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1718 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1720 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1722 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1730 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1731 u32 l, alpha_width = pll_alpha_width(pll);
1742 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1743 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1746 return wait_for_pll_enable_lock(pll);
1763 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1767 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1776 return wait_for_pll_enable_lock(pll);
1780 ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
1784 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1788 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1790 ret = wait_for_pll_enable_lock(pll);
1795 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1800 return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1805 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1809 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1820 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1825 ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1830 regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1839 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1845 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1874 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1875 struct regmap *regmap = pll->clkr.regmap;
1883 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
1890 if (!pll->post_div_table) {
1892 clk_hw_get_name(&pll->clkr.hw));
1897 for (i = 0; i < pll->num_post_div; i++) {
1898 if (pll->post_div_table[i].div == div) {
1899 val = pll->post_div_table[i].val;
1904 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1905 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1906 mask, val << pll->post_div_shift);
1942 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1945 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1946 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1947 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
1948 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
1949 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
1950 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1951 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
1952 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
1953 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
1954 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
1955 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
1957 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
1960 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1963 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1966 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1972 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1973 struct regmap *regmap = pll->clkr.regmap;
1977 regmap_read(regmap, PLL_MODE(pll), &val);
1984 return wait_for_pll_enable_active(pll);
1988 regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
1996 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1999 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2001 regmap_read(regmap, PLL_TEST_CTL(pll), &val);
2005 ret = wait_for_zonda_pll_freq_lock(pll);
2007 ret = wait_for_pll_enable_lock(pll);
2012 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2015 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2022 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2023 struct regmap *regmap = pll->clkr.regmap;
2026 regmap_read(regmap, PLL_MODE(pll), &val);
2035 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2038 regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
2041 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
2044 regmap_write(regmap, PLL_OPMODE(pll), 0x0);
2050 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2053 u32 l, alpha_width = pll_alpha_width(pll);
2063 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2064 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2070 regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
2074 ret = wait_for_zonda_pll_freq_lock(pll);
2076 ret = wait_for_pll_enable_lock(pll);
2095 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2101 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2102 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2103 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2104 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2105 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2106 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2107 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2108 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2109 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2110 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2111 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), config->test_ctl_hi2_val);
2114 regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2117 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2118 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2124 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2125 struct regmap *regmap = pll->clkr.regmap;
2129 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2138 return wait_for_pll_enable_lock(pll);
2142 ret = trion_pll_is_enabled(pll, regmap);
2146 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2150 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2155 regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2157 ret = wait_for_pll_enable_lock(pll);
2162 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2167 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2178 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2179 struct regmap *regmap = pll->clkr.regmap;
2183 ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2194 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2199 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2204 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2207 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, 0);
2212 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2218 regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2258 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2259 struct regmap *regmap = pll->clkr.regmap;
2262 regmap_read(regmap, PLL_L_VAL(pll), &l);
2264 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2266 return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2313 void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2316 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2317 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2318 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2319 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2320 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2321 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2322 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2323 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2325 regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2327 regmap_update_bits(regmap, PLL_MODE(pll),
2336 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2339 regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2347 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2353 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2356 min_freq = pll->vco_table[0].min_freq;
2357 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2371 void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2376 regmap_write(regmap, PLL_L_VAL(pll), config->l);
2377 regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2378 regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2380 if (pll_has_64bit_config(pll))
2381 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
2384 if (pll_alpha_width(pll) > 32)
2385 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
2407 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
2416 regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
2417 regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2418 regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2420 if (pll->flags & SUPPORTS_FSM_MODE)
2421 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
2440 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2447 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2448 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2449 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2452 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
2463 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2466 ret = wait_for_pll_update(pll);
2470 return wait_for_pll_enable_lock(pll);
2487 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2488 u32 l, alpha_width = pll_alpha_width(pll);
2494 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &pll_mode);
2498 regmap_write(pll->clkr.regmap, PLL_MODE(pll), 0);
2503 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
2508 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
2509 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2512 regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
2516 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
2522 ret = wait_for_pll_enable_lock(pll);
2530 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,