Lines Matching defs:ctl
615 u32 l, low, high, ctl;
622 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
623 if (ctl & PLL_ALPHA_EN) {
817 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
820 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
822 if (ctl & PLL_ALPHA_EN) {
841 if (!(ctl & PLL_ALPHA_MODE))
870 u32 l, a, ctl, cur_alpha = 0;
874 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
876 if (ctl & PLL_ALPHA_EN)
1071 u32 ctl;
1073 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1075 ctl >>= PLL_POST_DIV_SHIFT;
1076 ctl &= PLL_POST_DIV_MASK(pll);
1078 return parent_rate >> fls(ctl);
1118 u32 ctl, div;
1120 regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1122 ctl >>= PLL_POST_DIV_SHIFT;
1123 ctl &= BIT(pll->width) - 1;
1124 div = 1 << fls(ctl);