Lines Matching defs:clk
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
165 static struct clk *clk[LPC32XX_CLK_MAX];
167 .clks = clk,
171 static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
378 static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk)
383 static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val)
390 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
393 regmap_read(clk_regmap, clk->reg, &val);
395 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy)
398 return regmap_update_bits(clk_regmap, clk->reg,
399 clk->enable_mask, clk->enable);
404 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
406 regmap_update_bits(clk_regmap, clk->reg,
407 clk->disable_mask, clk->disable);
412 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
415 regmap_read(clk_regmap, clk->reg, &val);
417 return ((val & clk->enable_mask) == clk->enable);
428 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
431 regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable);
434 regmap_read(clk_regmap, clk->reg, &val);
447 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
449 regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0);
454 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
457 regmap_read(clk_regmap, clk->reg, &val);
459 val &= clk->enable | PLL_CTRL_LOCK;
460 if (val == (clk->enable | PLL_CTRL_LOCK))
475 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
480 regmap_read(clk_regmap, clk->reg, &val);
485 clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1;
486 clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1;
487 clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1;
490 clk->p_div = 0;
491 clk->mode = PLL_DIRECT_BYPASS;
495 clk->mode = PLL_BYPASS;
496 return parent_rate / (1 << clk->p_div);
499 clk->p_div = 0;
500 clk->mode = PLL_DIRECT;
503 ref_rate = parent_rate / clk->n_div;
504 rate = cco_rate = ref_rate * clk->m_div;
508 cco_rate *= (1 << clk->p_div);
509 clk->mode = PLL_INTEGER;
511 rate /= (1 << clk->p_div);
512 clk->mode = PLL_NON_INTEGER;
519 clk->n_div, clk->m_div, (1 << clk->p_div), rate);
535 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
540 switch (clk->mode) {
543 val |= (clk->m_div - 1) << 1;
544 val |= (clk->n_div - 1) << 9;
545 new_rate = (parent_rate * clk->m_div) / clk->n_div;
549 val |= (clk->p_div - 1) << 11;
550 new_rate = parent_rate / (1 << (clk->p_div));
558 val |= (clk->m_div - 1) << 1;
559 val |= (clk->n_div - 1) << 9;
560 val |= (clk->p_div - 1) << 11;
561 new_rate = (parent_rate * clk->m_div) / clk->n_div;
565 val |= (clk->m_div - 1) << 1;
566 val |= (clk->n_div - 1) << 9;
567 val |= (clk->p_div - 1) << 11;
568 new_rate = (parent_rate * clk->m_div) /
569 (clk->n_div * (1 << clk->p_div));
579 return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val);
585 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
623 clk->m_div = m;
624 clk->n_div = n;
625 clk->p_div = p;
629 clk->mode = PLL_DIRECT;
631 clk->mode = PLL_NON_INTEGER;
648 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
684 clk->n_div = n_i;
685 clk->m_div = m;
686 clk->p_div = 2;
687 clk->mode = PLL_NON_INTEGER;
715 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
718 regmap_read(clk_regmap, clk->reg, &val);
719 val &= clk->enable_mask | clk->busy_mask;
727 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
730 regmap_read(clk_regmap, clk->reg, &val);
731 hclk_div = val & clk->busy_mask;
741 return regmap_update_bits(clk_regmap, clk->reg,
742 clk->enable_mask, hclk_div << 7);
748 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
754 regmap_read(clk_regmap, clk->reg, &val);
755 val &= clk->enable_mask;
770 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
773 regmap_read(clk_regmap, clk->reg, &val);
799 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
802 pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable);
804 if (clk->ctrl_mask) {
807 clk->ctrl_mask, clk->ctrl_enable);
810 val = lpc32xx_usb_clk_read(clk);
811 if (clk->busy && (val & clk->busy) == clk->busy) {
812 if (clk->ctrl_mask)
818 val |= clk->enable;
819 lpc32xx_usb_clk_write(clk, val);
822 val = lpc32xx_usb_clk_read(clk);
823 if ((val & clk->enable) == clk->enable)
827 if ((val & clk->enable) == clk->enable)
830 if (clk->ctrl_mask)
838 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
839 u32 val = lpc32xx_usb_clk_read(clk);
841 val &= ~clk->enable;
842 lpc32xx_usb_clk_write(clk, val);
844 if (clk->ctrl_mask)
846 clk->ctrl_mask, clk->ctrl_disable);
851 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
854 if (clk->ctrl_mask) {
856 if ((ctrl_val & clk->ctrl_mask) != clk->ctrl_enable)
860 val = lpc32xx_usb_clk_read(clk);
862 return ((val & clk->enable) == clk->enable);
868 return clk_get_rate(clk[LPC32XX_CLK_PERIPH]);
886 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
887 u32 mask = BIT(clk->bit_idx);
888 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask);
890 return regmap_update_bits(clk_regmap, clk->reg, mask, val);
895 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
896 u32 mask = BIT(clk->bit_idx);
897 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0);
899 regmap_update_bits(clk_regmap, clk->reg, mask, val);
904 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
908 regmap_read(clk_regmap, clk->reg, &val);
909 is_set = val & BIT(clk->bit_idx);
911 return (clk->flags & CLK_GATE_SET_TO_DISABLE ? !is_set : is_set);
1059 struct lpc32xx_clk clk;
1173 .clk = { \
1382 static struct clk * __init lpc32xx_clk_register(u32 id)
1387 struct clk *clk;
1414 hw = &clk_hw->hw0.clk.hw;
1429 clk = clk_register(NULL, hw);
1443 mux_hw = &mux0->clk.hw;
1447 div_hw = &div0->clk.hw;
1451 gate_hw = &gate0->clk.hw;
1454 clk = clk_register_composite(NULL, lpc32xx_clk->name,
1464 clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name,
1469 clk = ERR_PTR(-EINVAL);
1472 return clk;
1492 struct clk *clk_osc, *clk_32k;
1540 clk[i] = lpc32xx_clk_register(i);
1541 if (IS_ERR(clk[i])) {
1543 clk_proto[i].name, PTR_ERR(clk[i]));
1544 clk[i] = NULL;
1551 clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000);
1554 clk_prepare_enable(clk[LPC32XX_CLK_ARM]);
1555 clk_prepare_enable(clk[LPC32XX_CLK_HCLK]);
1558 clk_prepare_enable(clk[LPC32XX_CLK_ARM_VFP]);
1561 clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_SLC].hw0.clk.hw);
1562 clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_MLC].hw0.clk.hw);
1564 CLK_OF_DECLARE(lpc32xx_clk, "nxp,lpc3220-clk", lpc32xx_clk_init);
1587 CLK_OF_DECLARE(lpc32xx_usb_clk, "nxp,lpc3220-usb-clk", lpc32xx_usb_clk_init);