Lines Matching refs:parent_rate
82 unsigned long parent_rate)
88 return parent_rate;
94 pll_freq = (u64)parent_rate * n;
99 static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long parent_rate)
105 return parent_rate;
112 pll_freq = (u64)parent_rate * n;
118 pll_freq = div_u64(parent_rate * n, 100 * m * p);
124 unsigned long parent_rate, u32 *reg_ctl,
148 tmp = div_u64(parent_rate, m);
153 fclk = div_u64(parent_rate * n, m);
186 unsigned long parent_rate)
193 if (parent_rate < PLL_FREF_MIN_FREQ || parent_rate > PLL_FREF_MAX_FREQ)
196 ret = ma35d1_pll_find_closest(pll, rate, parent_rate, reg_ctl, &pll_freq);
221 static unsigned long ma35d1_clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
227 if (parent_rate < PLL_FREF_MIN_FREQ || parent_rate > PLL_FREF_MAX_FREQ)
233 pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], parent_rate);
241 pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, parent_rate);
248 unsigned long *parent_rate)
255 if (*parent_rate < PLL_FREF_MIN_FREQ || *parent_rate > PLL_FREF_MAX_FREQ)
258 ret = ma35d1_pll_find_closest(pll, rate, *parent_rate, reg_ctl, &pll_freq);
265 pll_freq = ma35d1_calc_smic_pll_freq(reg_ctl[0], *parent_rate);
273 pll_freq = ma35d1_calc_pll_freq(pll->mode, reg_ctl, *parent_rate);