Lines Matching refs:dclk
33 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
35 val = readl_relaxed(dclk->reg) >> dclk->shift;
36 val &= clk_div_mask(dclk->width);
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table,
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
44 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
46 return divider_round_rate(hw, rate, prate, dclk->table,
47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
55 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
57 value = divider_get_val(rate, parent_rate, dclk->table,
58 dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
60 spin_lock_irqsave(dclk->lock, flags);
62 data = readl_relaxed(dclk->reg);
63 data &= ~(clk_div_mask(dclk->width) << dclk->shift);
64 data |= (value - 1) << dclk->shift;
65 data |= dclk->mask;
66 writel_relaxed(data, dclk->reg);
68 spin_unlock_irqrestore(dclk->lock, flags);