Lines Matching refs:data

610 	  .data = data_nb, },
612 .data = data_sb, },
616 static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
624 if (data->mux_hw) {
627 mux_hw = data->mux_hw;
634 if (data->gate_hw) {
637 gate_hw = data->gate_hw;
645 if (data->rate_hw) {
646 rate_hw = data->rate_hw;
648 if (data->is_double_div) {
667 if (data->muxrate_hw) {
669 struct clk_hw *muxrate_hw = data->muxrate_hw;
686 *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
687 data->num_parents, mux_hw,
696 struct clk_periph_driver_data *data = dev_get_drvdata(dev);
698 data->tbg_sel = readl(data->reg + TBG_SEL);
699 data->div_sel0 = readl(data->reg + DIV_SEL0);
700 data->div_sel1 = readl(data->reg + DIV_SEL1);
701 data->div_sel2 = readl(data->reg + DIV_SEL2);
702 data->clk_sel = readl(data->reg + CLK_SEL);
703 data->clk_dis = readl(data->reg + CLK_DIS);
710 struct clk_periph_driver_data *data = dev_get_drvdata(dev);
713 writel(data->clk_dis, data->reg + CLK_DIS);
714 writel(data->div_sel0, data->reg + DIV_SEL0);
715 writel(data->div_sel1, data->reg + DIV_SEL1);
716 writel(data->div_sel2, data->reg + DIV_SEL2);
717 writel(data->tbg_sel, data->reg + TBG_SEL);
718 writel(data->clk_sel, data->reg + CLK_SEL);
732 const struct clk_periph_data *data;
736 data = of_device_get_match_data(dev);
737 if (!data)
740 while (data[num_periph].name)
763 if (armada_3700_add_composite_clk(&data[i], driver_data->reg,
766 data[i].name);
783 struct clk_periph_driver_data *data = platform_get_drvdata(pdev);
784 struct clk_hw_onecell_data *hw_data = data->hw_data;