Lines Matching defs:APMU_GPU
63 #define APMU_GPU 0xcc
341 CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock},
343 CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock},
345 CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock},
357 {0, "gpu_3d_div", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 24, 4, 0, &gpu_lock},
358 {0, "gpu_2d_div", "gpu_2d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 28, 4, 0, &gpu_lock},
381 {MMP2_CLK_GPU_BUS, "gpu_bus_clk", "gpu_bus_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0xa, 0xa, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
386 {MMP2_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
391 {MMP3_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
392 {MMP3_CLK_GPU_2D, "gpu_2d_clk", "gpu_2d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x1c0000, 0x1c0000, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
442 pxa_unit->apmu_base + APMU_GPU,
449 pxa_unit->apmu_base + APMU_GPU,
486 pxa_unit->apmu_base + APMU_GPU,
491 pxa_unit->apmu_base + APMU_GPU,