Lines Matching refs:pll
16 #include "clk-pll.h"
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
40 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
43 int pcwbits = pll->data->pcwbits;
50 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
67 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll)
71 if (pll->tuner_en_addr) {
72 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
73 writel(r, pll->tuner_en_addr);
74 } else if (pll->tuner_addr) {
75 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
76 writel(r, pll->tuner_addr);
80 static void __mtk_pll_tuner_disable(struct mtk_clk_pll *pll)
84 if (pll->tuner_en_addr) {
85 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
86 writel(r, pll->tuner_en_addr);
87 } else if (pll->tuner_addr) {
88 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
89 writel(r, pll->tuner_addr);
93 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
99 __mtk_pll_tuner_disable(pll);
102 val = readl(pll->pd_addr);
103 val &= ~(POSTDIV_MASK << pll->data->pd_shift);
104 val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
107 if (pll->pd_addr != pll->pcw_addr) {
108 writel(val, pll->pd_addr);
109 val = readl(pll->pcw_addr);
113 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
114 pll->data->pcw_shift);
115 val |= pcw << pll->data->pcw_shift;
116 writel(val, pll->pcw_addr);
117 chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
118 writel(chg, pll->pcw_chg_addr);
119 if (pll->tuner_addr)
120 writel(val + 1, pll->tuner_addr);
123 __mtk_pll_tuner_enable(pll);
130 * @pll: The pll
137 void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
140 unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
141 const struct mtk_pll_div_table *div_table = pll->data->div_table;
146 if (freq > pll->data->fmax)
147 freq = pll->data->fmax;
167 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
168 _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
177 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
181 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
182 mtk_pll_set_rate_regs(pll, pcw, postdiv);
189 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
193 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
196 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
197 pcw &= GENMASK(pll->data->pcwbits - 1, 0);
199 return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
205 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
209 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
211 return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
216 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
219 r = readl(pll->pwr_addr) | CON0_PWR_ON;
220 writel(r, pll->pwr_addr);
223 r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
224 writel(r, pll->pwr_addr);
227 r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
228 writel(r, pll->en_addr);
230 if (pll->data->en_mask) {
231 r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
232 writel(r, pll->base_addr + REG_CON0);
235 __mtk_pll_tuner_enable(pll);
239 if (pll->data->flags & HAVE_RST_BAR) {
240 r = readl(pll->base_addr + REG_CON0);
241 r |= pll->data->rst_bar_mask;
242 writel(r, pll->base_addr + REG_CON0);
250 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
253 if (pll->data->flags & HAVE_RST_BAR) {
254 r = readl(pll->base_addr + REG_CON0);
255 r &= ~pll->data->rst_bar_mask;
256 writel(r, pll->base_addr + REG_CON0);
259 __mtk_pll_tuner_disable(pll);
261 if (pll->data->en_mask) {
262 r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
263 writel(r, pll->base_addr + REG_CON0);
266 r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
267 writel(r, pll->en_addr);
269 r = readl(pll->pwr_addr) | CON0_ISO_EN;
270 writel(r, pll->pwr_addr);
272 r = readl(pll->pwr_addr) & ~CON0_PWR_ON;
273 writel(r, pll->pwr_addr);
285 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
294 pll->base_addr = base + data->reg;
295 pll->pwr_addr = base + data->pwr_reg;
296 pll->pd_addr = base + data->pd_reg;
297 pll->pcw_addr = base + data->pcw_reg;
299 pll->pcw_chg_addr = base + data->pcw_chg_reg;
301 pll->pcw_chg_addr = pll->base_addr + REG_CON1;
303 pll->tuner_addr = base + data->tuner_reg;
305 pll->tuner_en_addr = base + data->tuner_en_reg;
307 pll->en_addr = base + data->en_reg;
309 pll->en_addr = pll->base_addr + REG_CON0;
310 pll->hw.init = &init;
311 pll->data = data;
322 ret = clk_hw_register(NULL, &pll->hw);
327 return &pll->hw;
333 struct mtk_clk_pll *pll;
336 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
337 if (!pll)
340 hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
342 kfree(pll);
349 struct mtk_clk_pll *pll;
354 pll = to_mtk_clk_pll(hw);
357 kfree(pll);
375 const struct mtk_pll_data *pll = &plls[i];
377 if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
379 node, pll->id);
383 hw = mtk_clk_register_pll(pll, base);
386 pr_err("Failed to register clk %s: %pe\n", pll->name,
391 clk_data->hws[pll->id] = hw;
398 const struct mtk_pll_data *pll = &plls[i];
400 mtk_clk_unregister_pll(clk_data->hws[pll->id]);
401 clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
413 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
415 return pll->base_addr - data->reg;
428 const struct mtk_pll_data *pll = &plls[i - 1];
430 if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
439 base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);
441 mtk_clk_unregister_pll(clk_data->hws[pll->id]);
442 clk_data->hws[pll->id] = ERR_PTR(-ENOENT);