Lines Matching defs:data
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
43 int pcwbits = pll->data->pcwbits;
50 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
72 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
85 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
103 val &= ~(POSTDIV_MASK << pll->data->pd_shift);
104 val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
113 val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
114 pll->data->pcw_shift);
115 val |= pcw << pll->data->pcw_shift;
140 unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
141 const struct mtk_pll_div_table *div_table = pll->data->div_table;
146 if (freq > pll->data->fmax)
147 freq = pll->data->fmax;
167 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
168 _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);
193 postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
196 pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
197 pcw &= GENMASK(pll->data->pcwbits - 1, 0);
227 r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
230 if (pll->data->en_mask) {
231 r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask;
239 if (pll->data->flags & HAVE_RST_BAR) {
241 r |= pll->data->rst_bar_mask;
253 if (pll->data->flags & HAVE_RST_BAR) {
255 r &= ~pll->data->rst_bar_mask;
261 if (pll->data->en_mask) {
262 r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask;
266 r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
286 const struct mtk_pll_data *data,
294 pll->base_addr = base + data->reg;
295 pll->pwr_addr = base + data->pwr_reg;
296 pll->pd_addr = base + data->pd_reg;
297 pll->pcw_addr = base + data->pcw_reg;
298 if (data->pcw_chg_reg)
299 pll->pcw_chg_addr = base + data->pcw_chg_reg;
302 if (data->tuner_reg)
303 pll->tuner_addr = base + data->tuner_reg;
304 if (data->tuner_en_reg || data->tuner_en_bit)
305 pll->tuner_en_addr = base + data->tuner_en_reg;
306 if (data->en_reg)
307 pll->en_addr = base + data->en_reg;
311 pll->data = data;
313 init.name = data->name;
314 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
316 if (data->parent_name)
317 init.parent_names = &data->parent_name;
330 struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
340 hw = mtk_clk_register_pll_ops(pll, data, base, &mtk_pll_ops);
411 const struct mtk_pll_data *data)
415 return pll->base_addr - data->reg;