Lines Matching defs:GATE_ICG1
427 #define GATE_ICG1(_id, _name, _parent, _shift) \
476 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_3, "infra_md2md_ccif_3", "axi_sel", 0),
477 GATE_ICG1(CLK_INFRA_SPI, "infra_spi", "spi_sel", 1),
478 GATE_ICG1(CLK_INFRA_MSDC0, "infra_msdc0", "msdc50_0_sel", 2),
479 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_4, "infra_md2md_ccif_4", "axi_sel", 3),
480 GATE_ICG1(CLK_INFRA_MSDC1, "infra_msdc1", "msdc30_1_sel", 4),
481 GATE_ICG1(CLK_INFRA_MSDC2, "infra_msdc2", "msdc30_2_sel", 5),
482 GATE_ICG1(CLK_INFRA_MD2MD_CCIF_5, "infra_md2md_ccif_5", "axi_sel", 7),
483 GATE_ICG1(CLK_INFRA_GCPU, "infra_gcpu", "axi_sel", 8),
484 GATE_ICG1(CLK_INFRA_TRNG, "infra_trng", "axi_sel", 9),
485 GATE_ICG1(CLK_INFRA_AUXADC, "infra_auxadc", "clk26m", 10),
486 GATE_ICG1(CLK_INFRA_CPUM, "infra_cpum", "axi_sel", 11),
487 GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_0, "infra_ap_c2k_ccif_0",
489 GATE_ICG1(CLK_INFRA_AP_C2K_CCIF_1, "infra_ap_c2k_ccif_1",
491 GATE_ICG1(CLK_INFRA_CLDMA, "infra_cldma", "axi_sel", 16),
492 GATE_ICG1(CLK_INFRA_DISP_PWM, "infra_disp_pwm", "pwm_sel", 17),
493 GATE_ICG1(CLK_INFRA_AP_DMA, "infra_ap_dma", "axi_sel", 18),
494 GATE_ICG1(CLK_INFRA_DEVICE_APC, "infra_device_apc", "axi_sel", 20),
495 GATE_ICG1(CLK_INFRA_L2C_SRAM, "infra_l2c_sram", "mm_sel", 22),
496 GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
497 GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
498 GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
535 GATE_ICG1(CLK_INFRA_MFG_VCG, "infra_mfg_vcg", "mfg_52m_sel", 14),