Lines Matching refs:GATE_PERI0
874 #define GATE_PERI0(_id, _name, _parent, _shift) \
885 GATE_PERI0(CLK_PERI_NFI, "per_nfi", "axi_sel", 0),
886 GATE_PERI0(CLK_PERI_THERM, "per_therm", "axi_sel", 1),
887 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", "pwm_sel", 2),
888 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3),
889 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4),
890 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5),
891 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6),
892 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7),
893 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8),
894 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9),
895 GATE_PERI0(CLK_PERI_PWM, "per_pwm", "pwm_sel", 10),
896 GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", "axi_sel", 13),
897 GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", "msdc50_0_sel", 14),
898 GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", "msdc30_1_sel", 15),
899 GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", "msdc30_2_sel", 16),
900 GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", "msdc30_3_sel", 17),
901 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20),
902 GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21),
903 GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22),
904 GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23),
905 GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", "axi_sel", 24),
906 GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", "axi_sel", 25),
907 GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", "axi_sel", 26),
908 GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", "axi_sel", 27),
909 GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", "axi_sel", 28),
910 GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", "ltepll_fs26m", 29),
911 GATE_PERI0(CLK_PERI_SPI0, "per_spi0", "spi_sel", 30),