Lines Matching refs:pll_info
85 const struct ingenic_cgu_pll_info *pll_info;
91 pll_info = &clk_info->pll;
93 ctl = readl(cgu->base + pll_info->reg);
95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
96 m += pll_info->m_offset;
97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
98 n += pll_info->n_offset;
100 if (pll_info->od_bits > 0) {
101 od_enc = ctl >> pll_info->od_shift;
102 od_enc &= GENMASK(pll_info->od_bits - 1, 0);
105 if (pll_info->bypass_bit >= 0) {
106 ctl = readl(cgu->base + pll_info->bypass_reg);
108 bypass = !!(ctl & BIT(pll_info->bypass_bit));
114 for (od = 0; od < pll_info->od_max; od++)
115 if (pll_info->od_encoding[od] == od_enc)
119 if (pll_info->od_max == 0)
120 BUG_ON(pll_info->od_bits != 0);
122 BUG_ON(od == pll_info->od_max);
125 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
130 ingenic_pll_calc_m_n_od(const struct ingenic_cgu_pll_info *pll_info,
141 n = min_t(unsigned int, n, 1 << pll_info->n_bits);
142 n = max_t(unsigned int, n, pll_info->n_offset);
145 m = min_t(unsigned int, m, 1 << pll_info->m_bits);
146 m = max_t(unsigned int, m, pll_info->m_offset);
158 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
161 if (pll_info->calc_m_n_od)
162 (*pll_info->calc_m_n_od)(pll_info, rate, parent_rate, &m, &n, &od);
164 ingenic_pll_calc_m_n_od(pll_info, rate, parent_rate, &m, &n, &od);
173 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
188 const struct ingenic_cgu_pll_info *pll_info)
192 if (pll_info->stable_bit < 0)
195 return readl_poll_timeout(cgu->base + pll_info->reg, ctl,
196 ctl & BIT(pll_info->stable_bit),
207 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
220 ctl = readl(cgu->base + pll_info->reg);
222 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);
223 ctl |= (m - pll_info->m_offset) << pll_info->m_shift;
225 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);
226 ctl |= (n - pll_info->n_offset) << pll_info->n_shift;
228 if (pll_info->od_bits > 0) {
229 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
230 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
233 writel(ctl, cgu->base + pll_info->reg);
235 if (pll_info->set_rate_hook)
236 pll_info->set_rate_hook(pll_info, rate, parent_rate);
239 if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit)))
240 ret = ingenic_pll_check_stable(cgu, pll_info);
252 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
257 if (pll_info->enable_bit < 0)
261 if (pll_info->bypass_bit >= 0) {
262 ctl = readl(cgu->base + pll_info->bypass_reg);
264 ctl &= ~BIT(pll_info->bypass_bit);
266 writel(ctl, cgu->base + pll_info->bypass_reg);
269 ctl = readl(cgu->base + pll_info->reg);
271 ctl |= BIT(pll_info->enable_bit);
273 writel(ctl, cgu->base + pll_info->reg);
275 ret = ingenic_pll_check_stable(cgu, pll_info);
286 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
290 if (pll_info->enable_bit < 0)
294 ctl = readl(cgu->base + pll_info->reg);
296 ctl &= ~BIT(pll_info->enable_bit);
298 writel(ctl, cgu->base + pll_info->reg);
307 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
310 if (pll_info->enable_bit < 0)
313 ctl = readl(cgu->base + pll_info->reg);
315 return !!(ctl & BIT(pll_info->enable_bit));