Lines Matching refs:cgu
23 #include "cgu.h"
30 return &clk->cgu->clock_info[clk->idx];
35 * @cgu: reference to the CGU whose registers should be read
39 * caller must hold cgu->lock.
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu,
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit))
53 * @cgu: reference to the CGU whose registers should be modified
59 * The caller must hold cgu->lock.
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu,
65 u32 clkgr = readl(cgu->base + info->reg);
72 writel(clkgr, cgu->base + info->reg);
84 struct ingenic_cgu *cgu = ingenic_clk->cgu;
93 ctl = readl(cgu->base + pll_info->reg);
106 ctl = readl(cgu->base + pll_info->bypass_reg);
187 static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu,
195 return readl_poll_timeout(cgu->base + pll_info->reg, ctl,
205 struct ingenic_cgu *cgu = ingenic_clk->cgu;
216 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n",
219 spin_lock_irqsave(&cgu->lock, flags);
220 ctl = readl(cgu->base + pll_info->reg);
233 writel(ctl, cgu->base + pll_info->reg);
240 ret = ingenic_pll_check_stable(cgu, pll_info);
242 spin_unlock_irqrestore(&cgu->lock, flags);
250 struct ingenic_cgu *cgu = ingenic_clk->cgu;
260 spin_lock_irqsave(&cgu->lock, flags);
262 ctl = readl(cgu->base + pll_info->bypass_reg);
266 writel(ctl, cgu->base + pll_info->bypass_reg);
269 ctl = readl(cgu->base + pll_info->reg);
273 writel(ctl, cgu->base + pll_info->reg);
275 ret = ingenic_pll_check_stable(cgu, pll_info);
276 spin_unlock_irqrestore(&cgu->lock, flags);
284 struct ingenic_cgu *cgu = ingenic_clk->cgu;
293 spin_lock_irqsave(&cgu->lock, flags);
294 ctl = readl(cgu->base + pll_info->reg);
298 writel(ctl, cgu->base + pll_info->reg);
299 spin_unlock_irqrestore(&cgu->lock, flags);
305 struct ingenic_cgu *cgu = ingenic_clk->cgu;
313 ctl = readl(cgu->base + pll_info->reg);
336 struct ingenic_cgu *cgu = ingenic_clk->cgu;
341 reg = readl(cgu->base + clk_info->mux.reg);
362 struct ingenic_cgu *cgu = ingenic_clk->cgu;
390 spin_lock_irqsave(&cgu->lock, flags);
393 reg = readl(cgu->base + clk_info->mux.reg);
396 writel(reg, cgu->base + clk_info->mux.reg);
398 spin_unlock_irqrestore(&cgu->lock, flags);
410 struct ingenic_cgu *cgu = ingenic_clk->cgu;
419 div_reg = readl(cgu->base + clk_info->div.reg);
513 static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu,
518 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,
529 struct ingenic_cgu *cgu = ingenic_clk->cgu;
547 spin_lock_irqsave(&cgu->lock, flags);
548 reg = readl(cgu->base + clk_info->div.reg);
564 writel(reg, cgu->base + clk_info->div.reg);
568 ret = ingenic_clk_check_stable(cgu, clk_info);
570 spin_unlock_irqrestore(&cgu->lock, flags);
581 struct ingenic_cgu *cgu = ingenic_clk->cgu;
586 spin_lock_irqsave(&cgu->lock, flags);
587 ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
588 spin_unlock_irqrestore(&cgu->lock, flags);
601 struct ingenic_cgu *cgu = ingenic_clk->cgu;
606 spin_lock_irqsave(&cgu->lock, flags);
607 ingenic_cgu_gate_set(cgu, &clk_info->gate, true);
608 spin_unlock_irqrestore(&cgu->lock, flags);
616 struct ingenic_cgu *cgu = ingenic_clk->cgu;
620 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
642 static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)
644 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];
655 clk = of_clk_get_by_name(cgu->np, clk_info->name);
667 cgu->clocks.clks[idx] = clk;
684 ingenic_clk->cgu = cgu;
712 parent = cgu->clocks.clks[clk_info->parents[i]];
723 parent = cgu->clocks.clks[clk_info->parents[0]];
778 cgu->clocks.clks[idx] = clk;
789 struct ingenic_cgu *cgu;
791 cgu = kzalloc(sizeof(*cgu), GFP_KERNEL);
792 if (!cgu)
795 cgu->base = of_iomap(np, 0);
796 if (!cgu->base) {
801 cgu->np = np;
802 cgu->clock_info = clock_info;
803 cgu->clocks.clk_num = num_clocks;
805 spin_lock_init(&cgu->lock);
807 return cgu;
810 kfree(cgu);
815 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu)
820 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *),
822 if (!cgu->clocks.clks) {
827 for (i = 0; i < cgu->clocks.clk_num; i++) {
828 err = ingenic_register_clock(cgu, i);
833 err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get,
834 &cgu->clocks);
841 for (i = 0; i < cgu->clocks.clk_num; i++) {
842 if (!cgu->clocks.clks[i])
844 if (cgu->clock_info[i].type & CGU_CLK_EXT)
845 clk_put(cgu->clocks.clks[i]);
847 clk_unregister(cgu->clocks.clks[i]);
849 kfree(cgu->clocks.clks);