Lines Matching defs:clk_info
83 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
90 BUG_ON(clk_info->type != CGU_CLK_PLL);
91 pll_info = &clk_info->pll;
154 ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
158 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
182 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
184 return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL);
206 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
207 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
213 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate,
217 clk_info->name, req_rate, rate);
251 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
252 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
285 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
286 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
306 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
307 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
335 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
340 if (clk_info->type & CGU_CLK_MUX) {
341 reg = readl(cgu->base + clk_info->mux.reg);
342 hw_idx = (reg >> clk_info->mux.shift) &
343 GENMASK(clk_info->mux.bits - 1, 0);
350 if (clk_info->parents[i] != -1)
361 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
367 if (clk_info->type & CGU_CLK_MUX) {
372 * clk_info->parents which does not equal -1.
375 num_poss = 1 << clk_info->mux.bits;
377 if (clk_info->parents[hw_idx] == -1)
387 mask = GENMASK(clk_info->mux.bits - 1, 0);
388 mask <<= clk_info->mux.shift;
393 reg = readl(cgu->base + clk_info->mux.reg);
395 reg |= hw_idx << clk_info->mux.shift;
396 writel(reg, cgu->base + clk_info->mux.reg);
409 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
415 if (clk_info->type & CGU_CLK_DIV) {
418 if (!(clk_info->div.bypass_mask & BIT(parent))) {
419 div_reg = readl(cgu->base + clk_info->div.reg);
420 div = (div_reg >> clk_info->div.shift) &
421 GENMASK(clk_info->div.bits - 1, 0);
423 if (clk_info->div.div_table)
424 div = clk_info->div.div_table[div];
426 div = (div + 1) * clk_info->div.div;
430 } else if (clk_info->type & CGU_CLK_FIXDIV) {
431 rate /= clk_info->fixdiv.div;
438 ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info,
443 for (i = 0; i < (1 << clk_info->div.bits)
444 && clk_info->div.div_table[i]; i++) {
445 if (clk_info->div.div_table[i] >= div &&
446 clk_info->div.div_table[i] < best) {
447 best = clk_info->div.div_table[i];
460 const struct ingenic_cgu_clk_info *clk_info,
467 if (clk_info->div.bypass_mask & BIT(parent))
473 if (clk_info->div.div_table) {
474 hw_div = ingenic_clk_calc_hw_div(clk_info, div);
476 return clk_info->div.div_table[hw_div];
480 div = clamp_t(unsigned int, div, clk_info->div.div,
481 clk_info->div.div << clk_info->div.bits);
488 div = DIV_ROUND_UP(div, clk_info->div.div);
489 div *= clk_info->div.div;
498 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
501 if (clk_info->type & CGU_CLK_DIV)
502 div = ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate,
504 else if (clk_info->type & CGU_CLK_FIXDIV)
505 div = clk_info->fixdiv.div;
514 const struct ingenic_cgu_clk_info *clk_info)
518 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,
519 !(reg & BIT(clk_info->div.busy_bit)),
528 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
535 if (clk_info->type & CGU_CLK_DIV) {
536 div = ingenic_clk_calc_div(hw, clk_info, parent_rate, req_rate);
542 if (clk_info->div.div_table)
543 hw_div = ingenic_clk_calc_hw_div(clk_info, div);
545 hw_div = ((div / clk_info->div.div) - 1);
548 reg = readl(cgu->base + clk_info->div.reg);
551 mask = GENMASK(clk_info->div.bits - 1, 0);
552 reg &= ~(mask << clk_info->div.shift);
553 reg |= hw_div << clk_info->div.shift;
556 if (clk_info->div.stop_bit != -1)
557 reg &= ~BIT(clk_info->div.stop_bit);
560 if (clk_info->div.ce_bit != -1)
561 reg |= BIT(clk_info->div.ce_bit);
564 writel(reg, cgu->base + clk_info->div.reg);
567 if (clk_info->div.busy_bit != -1)
568 ret = ingenic_clk_check_stable(cgu, clk_info);
580 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
584 if (clk_info->type & CGU_CLK_GATE) {
587 ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
590 if (clk_info->gate.delay_us)
591 udelay(clk_info->gate.delay_us);
600 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
604 if (clk_info->type & CGU_CLK_GATE) {
607 ingenic_cgu_gate_set(cgu, &clk_info->gate, true);
615 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
619 if (clk_info->type & CGU_CLK_GATE)
620 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
644 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];
652 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names));
654 if (clk_info->type == CGU_CLK_EXT) {
655 clk = of_clk_get_by_name(cgu->np, clk_info->name);
658 __func__, clk_info->name);
662 err = clk_register_clkdev(clk, clk_info->name, NULL);
671 if (!clk_info->type) {
673 clk_info->name);
687 clk_init.name = clk_info->name;
688 clk_init.flags = clk_info->flags;
691 caps = clk_info->type;
704 num_possible = 1 << clk_info->mux.bits;
706 num_possible = ARRAY_SIZE(clk_info->parents);
709 if (clk_info->parents[i] == -1)
712 parent = cgu->clocks.clks[clk_info->parents[i]];
721 BUG_ON(clk_info->parents[0] == -1);
723 parent = cgu->clocks.clks[clk_info->parents[0]];
728 clk_init.ops = clk_info->custom.clk_ops;
769 clk_info->name);
774 err = clk_register_clkdev(clk, clk_info->name, NULL);