Lines Matching refs:reg
107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
115 #define imx_clk_pfd(name, parent_name, reg, idx) \
116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
127 #define imx_clk_divider(name, parent, reg, shift, width) \
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
130 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
131 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
133 #define imx_clk_gate(name, parent, reg, shift) \
134 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
136 #define imx_clk_gate_dis(name, parent, reg, shift) \
137 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
139 #define imx_clk_gate2(name, parent, reg, shift) \
140 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
142 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
143 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
145 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
146 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
148 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
149 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
151 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
152 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
154 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
155 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
163 #define imx_clk_hw_gate(name, parent, reg, shift) \
164 imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
166 #define imx_clk_hw_gate2(name, parent, reg, shift) \
167 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
169 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \
170 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
172 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \
173 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
175 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \
176 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
178 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \
179 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
181 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \
182 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
184 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \
185 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
187 #define imx_clk_hw_gate3(name, parent, reg, shift) \
188 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
190 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \
191 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
193 #define imx_clk_hw_gate4(name, parent, reg, shift) \
194 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
196 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \
197 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
199 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \
200 imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
202 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \
203 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
205 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
206 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
208 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \
209 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
211 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
212 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
214 #define imx_clk_hw_divider(name, parent, reg, shift, width) \
215 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
217 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \
218 __imx_clk_hw_divider(name, parent, reg, shift, width, \
221 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \
222 __imx_clk_hw_divider(name, parent, reg, shift, width, flags)
285 void __iomem *reg, u8 bit_idx, u8 cgr_val, u8 cgr_mask,
301 void __iomem *reg, u8 shift, u32 exclusive_mask);
304 void __iomem *reg, u8 idx);
307 const char *parent_name, void __iomem *reg, u8 idx);
310 void __iomem *reg, u8 shift, u8 width,
313 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
321 void __iomem *reg);
327 void __iomem *reg, bool has_swrst);
330 void __iomem *reg, u8 shift, u8 width,
333 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
358 void __iomem *reg, u8 shift,
362 reg, shift, width, CLK_DIVIDER_ROUND_CLOSEST, &imx_ccm_lock);
367 void __iomem *reg, u8 shift,
371 reg, shift, width, 0, &imx_ccm_lock);
375 void __iomem *reg, u8 shift,
379 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
384 void __iomem *reg, u8 shift, u8 cgr_val,
388 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
392 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg,
397 flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
421 void __iomem *reg,
425 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \
427 ARRAY_SIZE(parent_names), reg, composite_flags, flags)
429 #define imx8m_clk_hw_composite(name, parent_names, reg) \
430 _imx8m_clk_hw_composite(name, parent_names, reg, \
433 #define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \
434 _imx8m_clk_hw_composite(name, parent_names, reg, \
437 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
438 _imx8m_clk_hw_composite(name, parent_names, reg, \
441 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
442 _imx8m_clk_hw_composite(name, parent_names, reg, \
445 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \
446 _imx8m_clk_hw_composite(name, parent_names, reg, \
449 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \
450 _imx8m_clk_hw_composite(name, parent_names, reg, \
453 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
454 _imx8m_clk_hw_composite(name, parent_names, reg, \
458 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
459 _imx8m_clk_hw_composite(name, parent_names, reg, \
466 void __iomem *reg,
469 #define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \
470 imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \
474 unsigned long flags, void __iomem *reg, u32 bit_idx, u32 val,
478 unsigned long flags, void __iomem *reg, u8 shift, u8 width,
483 u32 reg, const char **parent_names,