Lines Matching refs:parent
118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
124 #define imx_clk_fixed_factor(name, parent, mult, div) \
125 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
127 #define imx_clk_divider(name, parent, reg, shift, width) \
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
130 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
131 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
133 #define imx_clk_gate(name, parent, reg, shift) \
134 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
136 #define imx_clk_gate_dis(name, parent, reg, shift) \
137 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
139 #define imx_clk_gate2(name, parent, reg, shift) \
140 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
142 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
143 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
145 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
146 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
157 #define imx_clk_pllv1(type, name, parent, base) \
158 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
160 #define imx_clk_pllv2(name, parent, base) \
161 to_clk(imx_clk_hw_pllv2(name, parent, base))
163 #define imx_clk_hw_gate(name, parent, reg, shift) \
164 imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
166 #define imx_clk_hw_gate2(name, parent, reg, shift) \
167 imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
169 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \
170 imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
172 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \
173 __imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
175 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \
176 __imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
178 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \
179 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
181 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \
182 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
184 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \
185 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
187 #define imx_clk_hw_gate3(name, parent, reg, shift) \
188 imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
190 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \
191 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
193 #define imx_clk_hw_gate4(name, parent, reg, shift) \
194 imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
196 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \
197 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
214 #define imx_clk_hw_divider(name, parent, reg, shift, width) \
215 __imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
217 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \
218 __imx_clk_hw_divider(name, parent, reg, shift, width, \
221 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \
222 __imx_clk_hw_divider(name, parent, reg, shift, width, flags)
232 const char *parent, void __iomem *base);
234 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
243 u8 parent, u8 bypass1, u8 bypass2,
300 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
329 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
350 const char *parent, unsigned int mult, unsigned int div)
352 return clk_hw_register_fixed_factor(NULL, name, parent,
357 const char *parent,
361 return clk_hw_register_divider(NULL, name, parent, 0,
366 const char *parent,
370 return clk_hw_register_divider(NULL, name, parent, flags,
374 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent,
379 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
383 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent,
388 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,