Lines Matching defs:to_clk
105 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
109 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
113 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
116 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
119 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
122 to_clk(imx_clk_hw_fixed(name, rate))
125 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
128 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
131 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
134 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
137 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
140 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
143 to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
146 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
149 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
152 to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
155 to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
158 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
161 to_clk(imx_clk_hw_pllv2(name, parent, base))
337 static inline struct clk *to_clk(struct clk_hw *hw)