Lines Matching refs:reg
36 prediv_value = readl(divider->reg) >> divider->shift;
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
109 orig = readl(divider->reg);
117 writel(val, divider->reg);
135 val = readl(divider->reg);
171 u32 reg;
176 reg = readl(mux->reg);
177 reg &= ~(mux->mask << mux->shift);
179 reg |= val;
184 writel(reg, mux->reg);
185 writel(reg, mux->reg);
209 int num_parents, void __iomem *reg,
226 mux->reg = reg;
236 div->reg = reg;
266 gate->reg = reg;