Lines Matching defs:ops
58 const struct clk_ops *ops;
207 if (!core->ops->is_prepared)
211 ret = core->ops->is_prepared(core->hw);
226 if (!core->ops->is_enabled)
258 ret = core->ops->is_enabled(core->hw);
970 if (core->ops->unprepare)
971 core->ops->unprepare(core->hw);
1025 if (core->ops->prepare)
1026 ret = core->ops->prepare(core->hw);
1105 if (core->ops->disable)
1106 core->ops->disable(core->hw);
1164 if (core->ops->enable)
1165 ret = core->ops->enable(core->hw);
1206 core->ops->enable(hw);
1208 core->ops->disable(hw);
1223 if (core->ops && core->ops->save_context)
1224 ret = core->ops->save_context(core->hw);
1233 if (core->ops && core->ops->restore_context)
1234 core->ops->restore_context(core->hw);
1313 * making clk_enable()/clk_disable() no-ops, false otherwise.
1325 return clk && !(clk->core->ops->enable && clk->core->ops->disable);
1370 if (core->ops->unprepare_unused)
1371 core->ops->unprepare_unused(core->hw);
1372 else if (core->ops->unprepare)
1373 core->ops->unprepare(core->hw);
1411 if (core->ops->disable_unused)
1412 core->ops->disable_unused(core->hw);
1413 else if (core->ops->disable)
1414 core->ops->disable(core->hw);
1497 } else if (core->ops->determine_rate) {
1498 return core->ops->determine_rate(core->hw, req);
1499 } else if (core->ops->round_rate) {
1500 rate = core->ops->round_rate(core->hw, req->rate,
1590 return core->ops->determine_rate || core->ops->round_rate;
1781 if (core->ops->recalc_accuracy)
1782 core->accuracy = core->ops->recalc_accuracy(core->hw,
1828 if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
1829 rate = core->ops->recalc_rate(core->hw, parent_rate);
2087 if (parent && core->ops->set_parent)
2088 ret = core->ops->set_parent(core->hw, p_index);
2332 if (core->ops->set_rate_and_parent) {
2334 core->ops->set_rate_and_parent(core->hw, core->new_rate,
2337 } else if (core->ops->set_parent) {
2338 core->ops->set_parent(core->hw, core->new_parent_index);
2350 if (!skip_set_rate && core->ops->set_rate)
2351 core->ops->set_rate(core->hw, core->new_rate, best_parent_rate);
2718 if (core->num_parents > 1 && core->ops->get_parent)
2719 index = core->ops->get_parent(core->hw);
2775 /* verify ops for multi-parent clks */
2776 if (core->num_parents > 1 && !core->ops->set_parent)
2886 if (core->ops->set_phase) {
2887 ret = core->ops->set_phase(core->hw, degrees);
2950 if (!core->ops->get_phase)
2954 ret = core->ops->get_phase(core->hw);
2997 if (!core->ops->get_duty_cycle)
3000 ret = core->ops->get_duty_cycle(core->hw, duty);
3047 if (!core->ops->set_duty_cycle)
3050 ret = core->ops->set_duty_cycle(core->hw, duty);
3210 if (c->ops->is_enabled)
3212 else if (!c->ops->enable)
3595 if (core->ops->debug_init)
3596 core->ops->debug_init(core->hw, core->dentry);
3770 if (core->ops->set_rate &&
3771 !((core->ops->round_rate || core->ops->determine_rate) &&
3772 core->ops->recalc_rate)) {
3779 if (core->ops->set_parent && !core->ops->get_parent) {
3786 if (core->ops->set_parent && !core->ops->determine_rate) {
3793 if (core->num_parents > 1 && !core->ops->get_parent) {
3800 if (core->ops->set_rate_and_parent &&
3801 !(core->ops->set_parent && core->ops->set_rate)) {
3822 if (core->ops->init) {
3823 ret = core->ops->init(core->hw);
3858 if (core->ops->recalc_accuracy)
3859 core->accuracy = core->ops->recalc_accuracy(core->hw,
3890 if (core->ops->recalc_rate)
3891 rate = core->ops->recalc_rate(core->hw,
4178 if (WARN_ON(!init->ops)) {
4182 core->ops = init->ops;
4400 const struct clk_ops *ops;
4409 ops = clk->core->ops;
4410 if (ops == &clk_nodrv_ops) {
4416 * Assign empty clock ops for consumers that might still hold
4420 clk->core->ops = &clk_nodrv_ops;
4423 if (ops->terminate)
4424 ops->terminate(clk->core->hw);