Lines Matching refs:vc5
171 struct vc5_driver_data *vc5;
179 struct vc5_driver_data *vc5;
230 struct vc5_driver_data *vc5 =
236 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
248 dev_warn(&vc5->client->dev,
255 struct vc5_driver_data *vc5 =
260 if ((index > 1) || !vc5->clk_mux_ins)
263 if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
272 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
274 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
280 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
292 struct vc5_driver_data *vc5 =
297 ret = regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
319 struct vc5_driver_data *vc5 =
328 return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
342 struct vc5_driver_data *vc5 =
347 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
355 ret = regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
389 struct vc5_driver_data *vc5 =
397 ret = regmap_set_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
402 return regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
413 ret = regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
417 return regmap_clear_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
434 struct vc5_driver_data *vc5 = hwdata->vc5;
438 regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
451 struct vc5_driver_data *vc5 = hwdata->vc5;
455 rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max);
477 struct vc5_driver_data *vc5 = hwdata->vc5;
486 return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
499 struct vc5_driver_data *vc5 = hwdata->vc5;
506 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
508 regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
559 struct vc5_driver_data *vc5 = hwdata->vc5;
570 ret = regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
581 ret = regmap_clear_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
586 return regmap_set_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
599 struct vc5_driver_data *vc5 = hwdata->vc5;
614 if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) {
615 ret = regmap_set_bits(vc5->regmap,
626 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
632 ret = regmap_update_bits(vc5->regmap,
640 ret = regmap_set_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
646 dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n",
650 ret = regmap_update_bits(vc5->regmap,
664 struct vc5_driver_data *vc5 = hwdata->vc5;
667 regmap_clear_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
674 struct vc5_driver_data *vc5 = hwdata->vc5;
685 ret = regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
700 dev_warn(&vc5->client->dev,
708 struct vc5_driver_data *vc5 = hwdata->vc5;
722 return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
737 struct vc5_driver_data *vc5 = data;
740 if (idx >= vc5->chip_info->clk_out_cnt)
743 return &vc5->clk_out[idx].hw;
848 static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5)
866 ret = regmap_update_bits(vc5->regmap, VC5_XTAL_X1_LOAD_CAP, ~0x03,
871 return regmap_update_bits(vc5->regmap, VC5_XTAL_X2_LOAD_CAP, ~0x03,
946 struct vc5_driver_data *vc5;
952 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
953 if (!vc5)
956 i2c_set_clientdata(client, vc5);
957 vc5->client = client;
958 vc5->chip_info = i2c_get_match_data(client);
960 vc5->pin_xin = devm_clk_get(&client->dev, "xin");
961 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
964 vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
965 if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
968 vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
969 if (IS_ERR(vc5->regmap))
970 return dev_err_probe(&client->dev, PTR_ERR(vc5->regmap),
994 ret = regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, src_mask,
1002 if (!IS_ERR(vc5->pin_xin)) {
1003 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1004 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1005 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
1006 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
1009 if (IS_ERR(vc5->pin_xin))
1010 return PTR_ERR(vc5->pin_xin);
1011 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
1012 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
1015 if (!IS_ERR(vc5->pin_clkin)) {
1016 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
1018 __clk_get_name(vc5->pin_clkin);
1026 if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) {
1027 ret = vc5_update_cap_load(client->dev.of_node, vc5);
1041 vc5->clk_mux.init = &init;
1042 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
1047 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
1059 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1061 vc5->clk_mul.init = &init;
1062 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
1078 if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
1079 parent_names[0] = clk_hw_get_name(&vc5->clk_mul);
1081 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1083 vc5->clk_pfd.init = &init;
1084 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
1099 parent_names[0] = clk_hw_get_name(&vc5->clk_pfd);
1101 vc5->clk_pll.num = 0;
1102 vc5->clk_pll.vc5 = vc5;
1103 vc5->clk_pll.hw.init = &init;
1104 ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
1110 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
1111 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
1122 parent_names[0] = clk_hw_get_name(&vc5->clk_pll.hw);
1124 vc5->clk_fod[n].num = idx;
1125 vc5->clk_fod[n].vc5 = vc5;
1126 vc5->clk_fod[n].hw.init = &init;
1127 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
1144 parent_names[0] = clk_hw_get_name(&vc5->clk_mux);
1146 vc5->clk_out[0].num = idx;
1147 vc5->clk_out[0].vc5 = vc5;
1148 vc5->clk_out[0].hw.init = &init;
1149 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
1155 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
1156 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
1157 parent_names[0] = clk_hw_get_name(&vc5->clk_fod[idx].hw);
1159 parent_names[1] = clk_hw_get_name(&vc5->clk_mux);
1162 clk_hw_get_name(&vc5->clk_out[n - 1].hw);
1175 vc5->clk_out[n].num = idx;
1176 vc5->clk_out[n].vc5 = vc5;
1177 vc5->clk_out[n].hw.init = &init;
1178 ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[n].hw);
1184 ret = vc5_get_output_config(client, &vc5->clk_out[n]);
1189 ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
1203 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1204 clk_unregister_fixed_rate(vc5->pin_xin);
1210 struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
1214 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
1215 clk_unregister_fixed_rate(vc5->pin_xin);
1220 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1222 regcache_cache_only(vc5->regmap, true);
1223 regcache_mark_dirty(vc5->regmap);
1230 struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
1233 regcache_cache_only(vc5->regmap, false);
1234 ret = regcache_sync(vc5->regmap);
1334 .name = "vc5",