Lines Matching refs:clkdata
77 struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
80 if (regmap_read(clkdata->regmap, TPS68470_REG_PLLCTL, &val))
88 struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
90 regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1,
94 regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL,
108 struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
111 regmap_update_bits(clkdata->regmap, TPS68470_REG_PLLCTL, TPS68470_PLL_EN_MASK, 0);
114 regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG1, 0);
119 struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
121 return clkdata->rate;
160 struct tps68470_clkdata *clkdata = to_tps68470_clkdata(hw);
166 regmap_write(clkdata->regmap, TPS68470_REG_BOOSTDIV, clk_freqs[idx].boostdiv);
167 regmap_write(clkdata->regmap, TPS68470_REG_BUCKDIV, clk_freqs[idx].buckdiv);
168 regmap_write(clkdata->regmap, TPS68470_REG_PLLSWR, TPS68470_PLLSWR_DEFAULT);
169 regmap_write(clkdata->regmap, TPS68470_REG_XTALDIV, clk_freqs[idx].xtaldiv);
170 regmap_write(clkdata->regmap, TPS68470_REG_PLLDIV, clk_freqs[idx].plldiv);
171 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV, clk_freqs[idx].postdiv);
172 regmap_write(clkdata->regmap, TPS68470_REG_POSTDIV2, clk_freqs[idx].postdiv);
173 regmap_write(clkdata->regmap, TPS68470_REG_CLKCFG2, TPS68470_CLKCFG2_DRV_STR_2MA);
175 regmap_write(clkdata->regmap, TPS68470_REG_PLLCTL,
179 clkdata->rate = rate;