Lines Matching defs:cfg
327 void *cfg;
331 const struct clock_config *cfg);
391 const struct clock_config *cfg)
393 struct gate_cfg *gate_cfg = cfg->cfg;
396 cfg->name,
397 cfg->parent_name,
398 cfg->flags,
409 const struct clock_config *cfg)
411 struct fixed_factor_cfg *ff_cfg = cfg->cfg;
413 return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name,
414 cfg->flags, ff_cfg->mult,
422 const struct clock_config *cfg)
424 struct div_cfg *div_cfg = cfg->cfg;
427 cfg->name,
428 cfg->parent_name,
429 cfg->flags,
442 const struct clock_config *cfg)
444 struct mux_cfg *mux_cfg = cfg->cfg;
446 return clk_hw_register_mux(dev, cfg->name, cfg->parent_names,
447 cfg->num_parents, cfg->flags,
481 const struct stm32_mux_cfg *cfg,
488 if (cfg->mmux) {
493 mmux->mux.reg = cfg->mux->reg_off + base;
494 mmux->mux.shift = cfg->mux->shift;
495 mmux->mux.mask = (1 << cfg->mux->width) - 1;
496 mmux->mux.flags = cfg->mux->mux_flags;
497 mmux->mux.table = cfg->mux->table;
499 mmux->mmux = cfg->mmux;
501 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw;
508 mux->reg = cfg->mux->reg_off + base;
509 mux->shift = cfg->mux->shift;
510 mux->mask = (1 << cfg->mux->width) - 1;
511 mux->flags = cfg->mux->mux_flags;
512 mux->table = cfg->mux->table;
521 const struct stm32_div_cfg *cfg,
531 div->reg = cfg->div->reg_off + base;
532 div->shift = cfg->div->shift;
533 div->width = cfg->div->width;
534 div->flags = cfg->div->div_flags;
535 div->table = cfg->div->table;
542 const struct stm32_gate_cfg *cfg,
549 if (cfg->mgate) {
554 mgate->gate.reg = cfg->gate->reg_off + base;
555 mgate->gate.bit_idx = cfg->gate->bit_idx;
556 mgate->gate.flags = cfg->gate->gate_flags;
558 mgate->mask = BIT(cfg->mgate->nbr_clk++);
560 mgate->mgate = cfg->mgate;
569 gate->reg = cfg->gate->reg_off + base;
570 gate->bit_idx = cfg->gate->bit_idx;
571 gate->flags = cfg->gate->gate_flags;
587 const struct stm32_gate_cfg *cfg,
604 if (cfg->ops)
605 init.ops = cfg->ops;
607 hw = _get_stm32_gate(dev, base, cfg, lock);
625 const struct stm32_composite_cfg *cfg,
638 if (cfg->mux) {
639 mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock);
644 if (cfg->mux->ops)
645 mux_ops = cfg->mux->ops;
649 if (cfg->div) {
650 div_hw = _get_stm32_div(dev, base, cfg->div, lock);
655 if (cfg->div->ops)
656 div_ops = cfg->div->ops;
660 if (cfg->gate) {
661 gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock);
666 if (cfg->gate->ops)
667 gate_ops = cfg->gate->ops;
1111 const struct clock_config *cfg)
1113 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg;
1115 return clk_register_pll(dev, cfg->name, cfg->parent_names,
1116 cfg->num_parents,
1119 cfg->flags, lock);
1130 const struct clock_config *cfg)
1132 struct stm32_cktim_cfg *cktim_cfg = cfg->cfg;
1134 return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags,
1143 const struct clock_config *cfg)
1146 cfg->name,
1147 cfg->parent_name,
1148 cfg->parent_data,
1149 cfg->flags,
1151 cfg->cfg,
1159 const struct clock_config *cfg)
1161 return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,
1162 cfg->parent_data, cfg->num_parents,
1163 base, cfg->cfg, cfg->flags, lock);
1172 .cfg = &(struct gate_cfg) {\
1186 .cfg = &(struct fixed_factor_cfg) {\
1200 .cfg = &(struct div_cfg) {\
1221 .cfg = &(struct mux_cfg) {\
1237 .cfg = &(struct stm32_pll_cfg) {\
1250 .cfg = &(struct stm32_cktim_cfg) {\
1268 .cfg = (struct stm32_gate_cfg *) {_gate},\
1278 .cfg = (struct stm32_gate_cfg *) {_gate},\
1371 .cfg = &(struct stm32_composite_cfg) {\
2126 static bool stm32_check_security(const struct clock_config *cfg)
2131 if (cfg->id == stm32mp1_clock_secured[i])
2137 const struct clock_config *cfg;
2141 bool (*check_security)(const struct clock_config *cfg);
2145 .cfg = stm32mp1_clock_cfg,
2152 .cfg = stm32mp1_clock_cfg,
2175 const struct clock_config *cfg)
2182 if (cfg->func)
2183 hw = (*cfg->func)(dev, clk_data, base, lock, cfg);
2186 pr_err("Unable to register %s\n", cfg->name);
2190 if (cfg->id != NO_ID)
2191 hws[cfg->id] = hw;
2326 if (data->check_security && data->check_security(&data->cfg[n]))
2330 &data->cfg[n]);
2333 data->cfg[n].name, err);