Lines Matching defs:STM32F4_RCC_CFGR
29 #define STM32F4_RCC_CFGR 0x08
420 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
432 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
1183 STM32F4_RCC_CFGR, 23, 1,
1210 STM32F4_RCC_CFGR, 23, 1,
1255 STM32F4_RCC_CFGR, 23, 1,
1401 STM32F4_RCC_CFGR, 23, 1,
1785 base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1788 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1792 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1798 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1849 0, base + STM32F4_RCC_CFGR, 16, 5, 0,