Lines Matching defs:STM32F4_RCC_APB1ENR
33 #define STM32F4_RCC_APB1ENR 0x40
89 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
90 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
91 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
92 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
93 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
94 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
95 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
96 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
97 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
98 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
99 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
100 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
101 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
102 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
103 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
104 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
105 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
106 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
107 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
108 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
109 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
110 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
111 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
112 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
113 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
170 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
171 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
172 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
173 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
174 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
175 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
176 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
177 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
178 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
179 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
180 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
181 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
182 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
183 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
184 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
185 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
186 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
187 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
188 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
189 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
190 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
191 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
192 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
193 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
194 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
251 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
252 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
253 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
254 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
255 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
256 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
257 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
258 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
259 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
260 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
261 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
262 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
263 { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
264 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
265 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
266 { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
267 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
268 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
326 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
327 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
328 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
329 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
330 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
331 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
332 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
333 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
334 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
335 { STM32F4_RCC_APB1ENR, 10, "rtcapb", "apb1_mul" },
336 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
337 { STM32F4_RCC_APB1ENR, 13, "can3", "apb1_div" },
338 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
339 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
340 { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
341 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
342 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
343 { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
344 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
345 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
1308 STM32F4_RCC_APB1ENR, 17,
1315 STM32F4_RCC_APB1ENR, 18,
1322 STM32F4_RCC_APB1ENR, 19,
1329 STM32F4_RCC_APB1ENR, 20,
1344 STM32F4_RCC_APB1ENR, 30,
1351 STM32F4_RCC_APB1ENR, 31,
1358 STM32F4_RCC_APB1ENR, 21,
1365 STM32F4_RCC_APB1ENR, 22,
1372 STM32F4_RCC_APB1ENR, 23,
1379 STM32F4_RCC_APB1ENR, 24,
1387 STM32F4_RCC_APB1ENR, 9,
1460 STM32F4_RCC_APB1ENR, 17,
1467 STM32F4_RCC_APB1ENR, 18,
1474 STM32F4_RCC_APB1ENR, 19,
1481 STM32F4_RCC_APB1ENR, 20,
1495 STM32F4_RCC_APB1ENR, 30,
1502 STM32F4_RCC_APB1ENR, 31,
1509 STM32F4_RCC_APB1ENR, 21,
1516 STM32F4_RCC_APB1ENR, 22,
1523 STM32F4_RCC_APB1ENR, 23,
1530 STM32F4_RCC_APB1ENR, 24,
1537 STM32F4_RCC_APB1ENR, 9,