Lines Matching defs:init
1392 struct clk_init_data init;
1492 memset(&init, 0, sizeof(init));
1493 init.name = si5351_input_names[0];
1494 init.ops = &si5351_xtal_ops;
1495 init.flags = 0;
1498 init.parent_names = &drvdata->pxtal_name;
1499 init.num_parents = 1;
1501 drvdata->xtal.init = &init;
1504 dev_err(&client->dev, "unable to register %s\n", init.name);
1510 memset(&init, 0, sizeof(init));
1511 init.name = si5351_input_names[1];
1512 init.ops = &si5351_clkin_ops;
1515 init.parent_names = &drvdata->pclkin_name;
1516 init.num_parents = 1;
1518 drvdata->clkin.init = &init;
1522 init.name);
1535 drvdata->pll[0].hw.init = &init;
1536 memset(&init, 0, sizeof(init));
1537 init.name = si5351_pll_names[0];
1538 init.ops = &si5351_pll_ops;
1539 init.flags = 0;
1540 init.parent_names = parent_names;
1541 init.num_parents = num_parents;
1544 dev_err(&client->dev, "unable to register %s\n", init.name);
1551 drvdata->pll[1].hw.init = &init;
1552 memset(&init, 0, sizeof(init));
1554 init.name = si5351_pll_names[2];
1555 init.ops = &si5351_vxco_ops;
1556 init.flags = 0;
1557 init.parent_names = NULL;
1558 init.num_parents = 0;
1560 init.name = si5351_pll_names[1];
1561 init.ops = &si5351_pll_ops;
1562 init.flags = 0;
1563 init.parent_names = parent_names;
1564 init.num_parents = num_parents;
1568 dev_err(&client->dev, "unable to register %s\n", init.name);
1594 drvdata->msynth[n].hw.init = &init;
1595 memset(&init, 0, sizeof(init));
1596 init.name = si5351_msynth_names[n];
1597 init.ops = &si5351_msynth_ops;
1598 init.flags = 0;
1600 init.flags |= CLK_SET_RATE_PARENT;
1601 init.parent_names = parent_names;
1602 init.num_parents = 2;
1607 init.name);
1622 drvdata->clkout[n].hw.init = &init;
1623 memset(&init, 0, sizeof(init));
1624 init.name = si5351_clkout_names[n];
1625 init.ops = &si5351_clkout_ops;
1626 init.flags = 0;
1628 init.flags |= CLK_SET_RATE_PARENT;
1629 init.parent_names = parent_names;
1630 init.num_parents = num_parents;
1635 init.name);