Lines Matching refs:config
123 /* XTAL config bits */
229 { 0x002B, 0x02 }, /* SPI config */
1205 /* Update bits for P divider and synth config */
1269 struct clk_si5341_output_config *config)
1276 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1295 config[num].out_cm_ampl_bits = 0x33;
1298 config[num].out_cm_ampl_bits = 0x13;
1301 config[num].out_cm_ampl_bits = 0x33;
1303 config[num].out_format_drv_bits |= 0xc0;
1311 config[num].out_format_drv_bits &= ~0x07;
1312 config[num].out_format_drv_bits |= val & 0x07;
1314 config[num].out_format_drv_bits |= 0x08;
1324 config[num].out_cm_ampl_bits &= 0xf0;
1325 config[num].out_cm_ampl_bits |= val & 0x0f;
1335 config[num].out_cm_ampl_bits &= 0x0f;
1336 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1340 config[num].out_format_drv_bits |= 0x10;
1342 config[num].synth_master =
1345 config[num].always_on =
1348 config[num].vdd_sel_bits = 0x08;
1354 config[num].vdd_sel_bits |= 0 << 4;
1357 config[num].vdd_sel_bits |= 1 << 4;
1360 config[num].vdd_sel_bits |= 2 << 4;
1373 config[num].vdd_sel_bits |= 2 << 4;
1560 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1611 err = si5341_dt_parse_dt(data, config);
1727 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1731 if (config[i].out_format_drv_bits & 0x07) {
1734 config[i].out_format_drv_bits);
1737 config[i].out_cm_ampl_bits);
1741 config[i].vdd_sel_bits);
1750 if (config[i].always_on)