Lines Matching defs:synth
59 /* The output stages can be connected to any synth (full mux) */
73 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
222 * The "known" settings like synth and output configuration are done later.
565 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
568 u8 index = synth->index;
570 err = regmap_read(synth->data->regmap,
578 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
586 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
595 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
596 u8 index = synth->index; /* In range 0..5 */
600 regmap_update_bits(synth->data->regmap,
603 regmap_update_bits(synth->data->regmap,
605 /* Disable clock input to synth (set to 1 to disable) */
606 regmap_update_bits(synth->data->regmap,
612 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
614 u8 index = synth->index;
618 err = regmap_update_bits(synth->data->regmap,
623 /* Enable clock input to synth (set bit to 0 to enable) */
624 err = regmap_update_bits(synth->data->regmap,
630 return regmap_update_bits(synth->data->regmap,
638 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
644 err = si5341_decode_44_32(synth->data->regmap,
645 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
656 f = synth->data->freq_vco;
669 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
673 f = synth->data->freq_vco;
678 f = synth->data->freq_vco;
686 static int si5341_synth_program(struct clk_si5341_synth *synth,
690 u8 index = synth->index;
692 err = si5341_encode_44_32(synth->data->regmap,
695 err = regmap_update_bits(synth->data->regmap,
700 return regmap_write(synth->data->regmap,
708 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
715 n_num = synth->data->freq_vco;
731 dev_dbg(&synth->data->i2c_client->dev,
733 synth->index, n_num, n_den,
736 return si5341_synth_program(synth, n_num, n_den, is_integer);
980 return &data->synth[idx].hw;
1205 /* Update bits for P divider and synth config */
1343 of_property_read_bool(child, "silabs,synth-master");
1706 data->synth[i].index = i;
1707 data->synth[i].data = data;
1708 data->synth[i].hw.init = &init;
1709 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1712 "synth N%u registration failed\n", i);