Lines Matching refs:cg
74 #define CG_VER3 4 /* version 3 cg: reg layout different */
81 void (*init_periph)(struct clockgen *cg);
102 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
104 if (cg->info.flags & CG_LITTLE_ENDIAN)
110 static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
114 if (cg->info.flags & CG_LITTLE_ENDIAN)
469 static void __init p2041_init_periph(struct clockgen *cg)
473 reg = ioread32be(&cg->guts->rcwsr[7]);
476 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
478 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
481 static void __init p4080_init_periph(struct clockgen *cg)
485 reg = ioread32be(&cg->guts->rcwsr[7]);
488 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
490 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
493 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
495 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
498 static void __init p5020_init_periph(struct clockgen *cg)
503 reg = ioread32be(&cg->guts->rcwsr[7]);
508 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
510 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
513 static void __init p5040_init_periph(struct clockgen *cg)
518 reg = ioread32be(&cg->guts->rcwsr[7]);
523 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
525 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
528 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
530 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
533 static void __init t1023_init_periph(struct clockgen *cg)
535 cg->fman[0] = cg->hwaccel[1];
538 static void __init t1040_init_periph(struct clockgen *cg)
540 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
543 static void __init t2080_init_periph(struct clockgen *cg)
545 cg->fman[0] = cg->hwaccel[0];
548 static void __init t4240_init_periph(struct clockgen *cg)
550 cg->fman[0] = cg->hwaccel[3];
551 cg->fman[1] = cg->hwaccel[4];
837 struct clockgen *cg;
858 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
869 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
894 static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
906 return &cg->pll[pll].div[div];
909 static struct clk * __init create_mux_common(struct clockgen *cg,
931 div = get_pll_div(cg, hwc, i);
957 hwc->cg = cg;
970 static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
982 if (cg->info.flags & CG_VER3)
983 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
985 hwc->reg = cg->regs + 0x20 * idx;
987 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
996 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
997 div = get_pll_div(cg, hwc, clksel);
1007 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
1009 if (cg->info.flags & CG_CMUX_GE_PLAT)
1014 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
1015 pct80_rate, "cg-cmux%d", idx);
1018 static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
1026 hwc->reg = cg->regs + 0x20 * idx + 0x10;
1027 hwc->info = cg->info.hwaccel[idx];
1029 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
1030 "cg-hwaccel%d", idx);
1033 static void __init create_muxes(struct clockgen *cg)
1037 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
1038 if (cg->info.cmux_to_group[i] < 0)
1040 if (cg->info.cmux_to_group[i] >=
1041 ARRAY_SIZE(cg->info.cmux_groups)) {
1046 cg->cmux[i] = create_one_cmux(cg, i);
1049 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
1050 if (!cg->info.hwaccel[i])
1053 cg->hwaccel[i] = create_one_hwaccel(cg, i);
1211 static void __init create_one_pll(struct clockgen *cg, int idx)
1215 struct clockgen_pll *pll = &cg->pll[idx];
1216 const char *input = "cg-sysclk";
1219 if (!(cg->info.pll_mask & (1 << idx)))
1222 if (cg->coreclk && idx != PLATFORM_PLL) {
1223 if (IS_ERR(cg->coreclk))
1226 input = "cg-coreclk";
1229 if (cg->info.flags & CG_VER3) {
1232 reg = cg->regs + 0x60080;
1235 reg = cg->regs + 0x80;
1238 reg = cg->regs + 0xa0;
1241 reg = cg->regs + 0x10080;
1244 reg = cg->regs + 0x100a0;
1252 reg = cg->regs + 0xc00;
1254 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1258 mult = cg_in(cg, reg);
1266 if ((cg->info.flags & CG_VER3) ||
1267 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1284 "cg-pll%d-div%d", idx, i + 1);
1303 static void __init create_plls(struct clockgen *cg)
1307 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1308 create_one_pll(cg, i);
1389 struct clockgen *cg = data;
1406 clk = cg->sysclk;
1409 if (idx >= ARRAY_SIZE(cg->cmux))
1411 clk = cg->cmux[idx];
1414 if (idx >= ARRAY_SIZE(cg->hwaccel))
1416 clk = cg->hwaccel[idx];
1419 if (idx >= ARRAY_SIZE(cg->fman))
1421 clk = cg->fman[idx];
1424 pll = &cg->pll[PLATFORM_PLL];
1432 clk = cg->coreclk;
1546 clockgen.sysclk = create_sysclk("cg-sysclk");
1547 clockgen.coreclk = create_coreclk("cg-coreclk");