Lines Matching defs:PLATFORM_PLL
29 #define PLATFORM_PLL 0
259 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
272 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
285 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
298 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
338 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
412 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
425 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
433 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
449 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
459 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
478 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
490 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
495 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
510 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
525 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
530 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
540 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
568 .pll_mask = BIT(PLATFORM_PLL) |
586 .pll_mask = BIT(PLATFORM_PLL) |
599 .pll_mask = BIT(PLATFORM_PLL) |
614 .pll_mask = BIT(PLATFORM_PLL) |
630 .pll_mask = BIT(PLATFORM_PLL) |
646 .pll_mask = BIT(PLATFORM_PLL) |
661 .pll_mask = BIT(PLATFORM_PLL) |
673 .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
683 .pll_mask = BIT(PLATFORM_PLL) |
696 .pll_mask = BIT(PLATFORM_PLL) |
711 .pll_mask = BIT(PLATFORM_PLL) |
724 .pll_mask = BIT(PLATFORM_PLL) |
737 .pll_mask = BIT(PLATFORM_PLL) |
751 .pll_mask = BIT(PLATFORM_PLL) |
764 .pll_mask = BIT(PLATFORM_PLL) |
780 .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
793 .pll_mask = BIT(PLATFORM_PLL) |
810 .pll_mask = BIT(PLATFORM_PLL) |
827 .pll_mask = BIT(PLATFORM_PLL) |
1007 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
1222 if (cg->coreclk && idx != PLATFORM_PLL) {
1231 case PLATFORM_PLL:
1251 if (idx == PLATFORM_PLL)
1267 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1280 if (idx != PLATFORM_PLL && i >= 4)
1363 legacy_pll_init(np, PLATFORM_PLL);
1424 pll = &cg->pll[PLATFORM_PLL];