Lines Matching defs:CLKSEL_VALID
47 #define CLKSEL_VALID 1
124 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
125 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
126 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
132 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
133 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
134 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
140 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
141 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
142 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
148 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
149 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
150 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
156 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
157 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
158 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
159 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
165 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
166 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
167 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
168 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
174 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
175 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
176 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
177 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
178 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
184 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
185 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
186 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
187 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
188 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
194 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
195 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
201 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
202 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
203 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
204 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
212 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
213 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
216 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
217 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
220 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
221 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
228 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
229 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
232 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
233 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
240 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
241 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
244 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
245 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
253 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
259 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
260 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
261 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
262 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
263 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
266 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
272 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
273 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
274 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
275 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
276 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
278 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
279 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
285 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
286 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
288 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
289 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
291 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
292 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
298 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
299 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
300 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
301 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
302 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
304 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
305 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
313 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
314 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
317 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
318 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
325 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
327 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
335 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
336 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
337 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
338 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
339 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
340 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
347 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
348 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
349 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
352 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
361 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
362 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
364 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
365 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
372 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
373 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
374 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
375 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
377 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
378 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
384 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
386 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
394 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
395 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
401 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
408 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
409 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
410 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
411 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
412 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
413 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
414 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
421 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
422 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
423 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
424 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
425 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
426 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
427 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
433 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
434 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
435 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
436 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
437 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
439 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
440 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
446 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
447 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
448 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
449 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
450 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
456 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
457 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
458 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
459 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
460 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
461 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
900 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))