Lines Matching defs:CGA_PLL3
32 #define CGA_PLL3 3
178 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
185 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
186 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
220 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
221 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
488 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
493 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
523 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
528 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
569 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
587 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
739 BIT(CGA_PLL3) | BIT(CGA_PLL4),
765 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3),
828 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |