Lines Matching defs:CGA_PLL2
31 #define CGA_PLL2 2
126 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
133 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
134 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
142 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
149 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
150 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
158 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
159 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
167 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
168 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
176 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
177 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
203 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
204 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
216 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
217 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
232 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
233 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
265 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
266 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
273 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
274 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
275 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
276 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
291 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
292 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
299 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
300 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
301 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
302 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
317 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
318 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
325 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
327 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
339 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
340 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
347 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
348 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
349 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
364 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
365 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
372 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
373 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
374 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
375 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
413 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
414 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
421 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
422 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
423 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
424 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
439 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
440 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
476 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
508 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
569 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
587 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
600 BIT(CGA_PLL1) | BIT(CGA_PLL2),
615 BIT(CGA_PLL1) | BIT(CGA_PLL2),
631 BIT(CGA_PLL1) | BIT(CGA_PLL2),
647 BIT(CGA_PLL1) | BIT(CGA_PLL2),
662 BIT(CGA_PLL1) | BIT(CGA_PLL2),
684 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
697 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
712 BIT(CGA_PLL1) | BIT(CGA_PLL2),
725 BIT(CGA_PLL1) | BIT(CGA_PLL2),
738 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
752 BIT(CGA_PLL1) | BIT(CGA_PLL2),
765 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3),
794 BIT(CGA_PLL1) | BIT(CGA_PLL2),
811 BIT(CGA_PLL1) | BIT(CGA_PLL2),
828 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
1237 case CGA_PLL2: