Lines Matching defs:data

67 	struct clk_plldig *data = to_clk_plldig(hw);
70 val = readl(data->regs + PLLDIG_REG_PLLFM);
76 writel(val, data->regs + PLLDIG_REG_PLLFM);
83 struct clk_plldig *data = to_clk_plldig(hw);
86 val = readl(data->regs + PLLDIG_REG_PLLFM);
91 writel(val, data->regs + PLLDIG_REG_PLLFM);
96 struct clk_plldig *data = to_clk_plldig(hw);
98 return readl(data->regs + PLLDIG_REG_PLLFM) &
105 struct clk_plldig *data = to_clk_plldig(hw);
108 val = readl(data->regs + PLLDIG_REG_PLLDV);
123 return DIV_ROUND_UP(data->vco_freq, rfdphi1);
140 struct clk_plldig *data = to_clk_plldig(hw);
144 div = plldig_calc_target_div(data->vco_freq, req->rate);
145 req->rate = DIV_ROUND_UP(data->vco_freq, div);
153 struct clk_plldig *data = to_clk_plldig(hw);
158 rfdphi1 = plldig_calc_target_div(data->vco_freq, rate);
161 val = readl(data->regs + PLLDIG_REG_PLLDV);
164 writel(val, data->regs + PLLDIG_REG_PLLDV);
170 return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,
186 struct clk_plldig *data = to_clk_plldig(hw);
198 if (data->vco_freq) {
199 mfd = data->vco_freq / parent_rate;
200 lltmp = data->vco_freq % parent_rate;
206 data->vco_freq = parent_rate * mfd;
210 writel(val, data->regs + PLLDIG_REG_PLLDV);
216 writel(val, data->regs + PLLDIG_REG_PLLFD);
224 struct clk_plldig *data;
228 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
229 if (!data)
232 data->regs = devm_platform_ioremap_resource(pdev, 0);
233 if (IS_ERR(data->regs))
234 return PTR_ERR(data->regs);
236 data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",
241 ret = devm_clk_hw_register(dev, &data->hw);
249 &data->hw);
260 &data->vco_freq)) {
261 if (data->vco_freq < PLLDIG_MIN_VCO_FREQ ||
262 data->vco_freq > PLLDIG_MAX_VCO_FREQ)
266 return plldig_init(&data->hw);