Lines Matching refs:x00
58 #define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00
78 #define LMK04832_VAL_VCO_MUX_VCO0 0x00
84 #define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00
97 #define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00
100 #define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P 0x00
118 #define LMK04832_VAL_SYNC_MODE_OFF 0x00
321 .write_flag_mask = 0x00,
351 0x00);
358 LMK04832_BIT_OSCIN_PD, 0x00);
766 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
785 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
803 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
862 LMK04832_BIT_SYSREF_PD, 0x00);
1033 LMK04832_BIT_DCLKX_Y_PD, 0x00);
1127 LMK04832_BIT_DCLK_DIV_MSB, 0x00);
1224 LMK04832_BIT_CLKOUTX_Y_PD, 0x00);
1236 LMK04832_BIT_SCLK_PD, 0x00);
1254 0x00);