Lines Matching defs:mult
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
28 rate = (unsigned long long int)parent_rate * fix->mult;
41 best_parent = (rate / fix->mult) * fix->div;
45 return (*prate / fix->div) * fix->mult;
83 unsigned long flags, unsigned int mult, unsigned int div,
105 fix->mult = mult;
144 * @mult: multiplier
152 unsigned int mult, unsigned int div)
155 flags, mult, div, true);
166 * @mult: multiplier
174 unsigned long flags, unsigned int mult, unsigned int div)
177 -1, flags, mult, div, true);
183 unsigned long flags, unsigned int mult, unsigned int div)
186 parent_hw, -1, flags, mult, div,
193 unsigned int mult, unsigned int div)
196 flags, mult, div, false);
202 unsigned int mult, unsigned int div)
206 hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,
240 unsigned int mult, unsigned int div)
243 flags, mult, div, true);
252 u32 div, mult;
261 if (of_property_read_u32(node, "clock-mult", &mult)) {
262 pr_err("%s Fixed factor clock <%pOFn> must have a clock-mult property\n",
270 0, mult, div, false);