Lines Matching refs:np_base
200 void __iomem *np_base = cg->base;
204 val = readl(np_base + REG_PCI_CONTROL);
206 writel(val, np_base + REG_PCI_CONTROL);
211 writel(val, np_base + REG_PCI_CONTROL);
215 val = readl(np_base + REG_RESET_CONTROL);
218 writel(val & ~mask, np_base + REG_RESET_CONTROL);
220 writel(val | mask, np_base + REG_RESET_CONTROL);
222 writel(val & ~mask, np_base + REG_RESET_CONTROL);
227 val = readl(np_base + REG_PCI_CONTROL);
228 writel(val & ~mask, np_base + REG_PCI_CONTROL);
230 writel(val | mask, np_base + REG_PCI_CONTROL);
239 void __iomem *np_base = cg->base;
242 val = readl(np_base + REG_PCI_CONTROL);
244 writel(val, np_base + REG_PCI_CONTROL);
248 void __iomem *np_base)
265 cg->base = np_base;
276 void __iomem *base, void __iomem *np_base)
298 hw = en7523_register_pcie_clk(dev, np_base);
308 void __iomem *base, *np_base;
315 np_base = devm_platform_ioremap_resource(pdev, 1);
316 if (IS_ERR(np_base))
317 return PTR_ERR(np_base);
325 en7523_register_clocks(&pdev->dev, clk_data, base, np_base);