Lines Matching refs:cdce
295 struct cdce706_dev_data *cdce = hwd->dev_data;
312 struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];
450 static int cdce706_register_hw(struct cdce706_dev_data *cdce,
460 hw->dev_data = cdce;
463 ret = devm_clk_hw_register(&cdce->client->dev,
466 dev_err(&cdce->client->dev, "Failed to register %s\n",
474 static int cdce706_register_clkin(struct cdce706_dev_data *cdce)
478 .parent_names = cdce->clkin_name,
479 .num_parents = ARRAY_SIZE(cdce->clkin_name),
485 for (i = 0; i < ARRAY_SIZE(cdce->clkin_name); ++i) {
486 struct clk *parent = devm_clk_get(&cdce->client->dev,
490 cdce->clkin_name[i] = cdce706_source_name[i];
492 cdce->clkin_name[i] = __clk_get_name(parent);
493 cdce->clkin_clk[i] = parent;
497 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_SOURCE, &source);
502 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_CLOCK, &clock);
505 cdce->clkin[0].parent = !!(clock & CDCE706_CLKIN_CLOCK_MASK);
508 ret = cdce706_register_hw(cdce, cdce->clkin,
509 ARRAY_SIZE(cdce->clkin),
514 static int cdce706_register_plls(struct cdce706_dev_data *cdce)
525 ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux);
529 for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) {
532 ret = cdce706_reg_read(cdce, CDCE706_PLL_M_LOW(i), &m);
535 ret = cdce706_reg_read(cdce, CDCE706_PLL_N_LOW(i), &n);
538 ret = cdce706_reg_read(cdce, CDCE706_PLL_HI(i), &v);
541 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8);
542 cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) <<
544 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i);
545 dev_dbg(&cdce->client->dev,
547 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux);
550 ret = cdce706_register_hw(cdce, cdce->pll,
551 ARRAY_SIZE(cdce->pll),
556 static int cdce706_register_dividers(struct cdce706_dev_data *cdce)
567 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) {
570 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER_PLL(i), &val);
573 cdce->divider[i].parent =
577 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER(i), &val);
580 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK;
581 dev_dbg(&cdce->client->dev,
583 cdce->divider[i].parent, cdce->divider[i].div);
586 ret = cdce706_register_hw(cdce, cdce->divider,
587 ARRAY_SIZE(cdce->divider),
592 static int cdce706_register_clkouts(struct cdce706_dev_data *cdce)
603 for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i) {
606 ret = cdce706_reg_read(cdce, CDCE706_CLKOUT(i), &val);
609 cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK;
610 dev_dbg(&cdce->client->dev,
612 cdce->clkout[i].parent);
615 return cdce706_register_hw(cdce, cdce->clkout,
616 ARRAY_SIZE(cdce->clkout),
623 struct cdce706_dev_data *cdce = data;
626 if (idx >= ARRAY_SIZE(cdce->clkout)) {
631 return &cdce->clkout[idx].hw;
637 struct cdce706_dev_data *cdce;
643 cdce = devm_kzalloc(&client->dev, sizeof(*cdce), GFP_KERNEL);
644 if (!cdce)
647 cdce->client = client;
648 cdce->regmap = devm_regmap_init_i2c(client, &cdce706_regmap_config);
649 if (IS_ERR(cdce->regmap)) {
654 i2c_set_clientdata(client, cdce);
656 ret = cdce706_register_clkin(cdce);
659 ret = cdce706_register_plls(cdce);
662 ret = cdce706_register_dividers(cdce);
665 ret = cdce706_register_clkouts(cdce);
669 cdce);